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| Freescale Semiconductor Technical Data Document Number: DSP56364 Rev. 4, 08/2006 DSP56364 24-Bit Audio Digital Signal Processor 1 Overview Contents 1 2 3 4 5 6 A Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Signal/Connection Descriptions . . . . . . . . . 2-1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Design Considerations . . . . . . . . . . . . . . . . 5-1 Ordering Information . . . . . . . . . . . . . . . . . . 6-1 IBIS Model . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 The DSP56364 supports digital audio applications requiring sound field processing, acoustic equalization, and other digital audio algorithms. The DSP56364 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Freescale SymphonyTM DSP family, as shown in Figure 1-1. This design provides a two-fold performance increase over Freescale's popular Symphony family of DSPs while retaining code compatibility. Significant architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct memory access (DMA). The DSP56364 offers 100 million instructions per second (MIPS) using an internal 100 MHz clock at 3.3 V. This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2006. All rights reserved. Overview Data Sheet Conventions This data sheet uses the following conventions: OVERBAR "asserted" "deasserted" Examples: Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage* VIL / VOL VIH / VOH VIH / VOH VIL / VOL Note: *Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. 4 12 5 GPIO ESAI SHI PROGRAM RAM 0.5K x 24 PROGRAM ROM 8K x 24 X MEMORY RAM 1K X 24 Y MEMORY RAM 1.5K X 24 PIO_EB PM_EB XM_EB YM_EB PERIPHERAL EXPANSION AREA ADDRESS GENERATION UNIT SIX CHANNELS DMA UNIT Bootstrap ROM 192 x 24 MEMORY EXPANSION AREA ADDRESS EXTERNAL ADDRESS BUS SWITCH 18 YAB XAB PAB DAB 24-BIT DSP56300 CORE DDB INTERNAL DATA BUS SWITCH YDB XDB PDB GDB DRAM & SRAM BUS INTERFACE CONTROL 6 EXTERNAL DATA BUS SWITCH DATA 8 POWER MGMT PLL CLOCK GEN PROGRAM INTERRUPT CONT PROGRAM DECODE CONT PROGRAM ADDRESS GEN DATA ALU 24 X 24+5656-BIT MAC TWO 56-BIT ACCUMULATORS BARREL SHIFTER 4 JTAG OnCETM EXTAL MODA/IRQA MODB/IRQB MODD/IRQD 24 BITS BUS RESET PINIT/NMI Figure 1-1 DSP56364 Block Diagram DSP56364 Technical Data, Rev. 4 1-2 Freescale Semiconductor Overview 1.1 1.1.1 * * * * * * * * * * Features Digital Signal Processing Core 100 Million Instructions Per Second (MIPS) with an 100 MHz clock at 3.3V. Object Code Compatible with the 56000 core. Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic support. Program Control with position independent code support and instruction cache support. Six-channel DMA controller. PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors (1 to 16) and power saving clock divider (2i: i=0 to 7). Reduces clock noise. Internal address tracing support and OnCETM for Hardware/Software debugging. JTAG port. Very low-power CMOS design, fully static design with operating frequencies down to DC. STOP and WAIT low-power standby modes. 1.1.2 * * * * * On-chip Memory Configuration 1.5Kx24 Bit Y-Data RAM. 1Kx24 Bit X-Data RAM. 8Kx24 Bit Program ROM. 0.5Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM. 0.75Kx24 Bit from Y Data RAM can be switched to Program RAM resulting in up to 1.25Kx24 Bit of Program RAM. 1.1.3 * * * * Off-chip memory expansion External Memory Expansion Port with 8-bit data bus. Off-chip expansion up to 2 x 16M x 8-bit word of Data/Program memory when using DRAM. Off-chip expansion up to 2 x 256k x 8-bit word of Data/Program memory when using SRAM. Simultaneous glueless interface to SRAM and DRAM. 1.1.4 * Peripheral modules Enhanced Serial Audio Interface (ESAI): 6 serial lines, 4 selectable as receive or transmitt and 2 transmitt only, master or slave. I2S, Sony, AC97, network and other programmable protocols. Unused pins of ESAI may be used as GPIO lines. Serial Host Interface (SHI): SPI and I2C protocols, 10-word receive FIFO, support for 8, 16 and 24-bit words. Four dedicated GPIO lines. * * DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 1-3 Overview 1.1.5 * Packaging 100-pin plastic TQFP package. 1.2 Documentation Table 1-1 lists the documents that provide a complete description of the DSP56364 and are required to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, a Freescale Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source for the latest information). Table 1-1 DSP56364 Documentation Document Name DSP56300 Family Manual Description Detailed description of the 56000-family architecture and the 24-bit core processor and instruction set Detailed description of memory, peripherals, and interfaces Brief description of the chip Electrical and timing specifications; pin and package descriptions Order Number DSP56300FM DSP56364 User's Manual DSP56364 Product Brief DSP56364 Technical Data Sheet (this document) DSP56364UM DSP56364P DSP56364 DSP56364 Technical Data, Rev. 4 1-4 Freescale Semiconductor 2 2.1 Signal/Connection Descriptions Signal Groupings The input and output signals of the DSP56364 are organized into functional groups, which are listed in Table 2-1 and illustrated in Figure 2-1. The DSP56364 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs. Table 2-1 DSP56364 Functional Signal Groupings Functional Group Power (VCC) Ground (GND) Clock and PLL Address bus Data bus Bus control Interrupt and mode control General Purpose I/O SHI ESAI JTAG/OnCE Port 1 2 Number of Signals 18 14 3 18 Port A1 8 6 4 Port B2 4 5 Port C3 12 4 Detailed Description Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 2-7 Table 2-8 Table 2-12 Table 2-9 Table 2-10 Table 2-11 Port A is the external memory interface port, including the external address bus, data bus, and control signals. Port B signals are the GPIO signals. 3 Port C signals are the ESAI port signals multiplexed with the GPIO signals. DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 2-1 Signal Groupings PORT A ADDRESS BUS A0-A17 VCCA (4) GNDA (4) OnCETM ON-CHIP EMULATION/ JTAG PORT DSP56364 Port B GPIO TDI TCK TDO TMS PORT A DATA BUS D0-D7 VCCD (1) GNDD (1) PB0-PB3 PORT A BUS CONTROL AA0-AA1/RAS0-RAS1 CAS RD WR TA VCCC (1) GNDC (1) RESERVED (4) SERIAL AUDIO INTERFACE (ESAI) Port C SCKT [PC3] FST [PC4] HCKT [PC5] SCKR [PC0] FSR [PC1] HCKR [PC2] SDO0 [PC11] SDO1 [PC10] SDO2/SDI3 [PC9] SDO3/SDI2 [PC8] SDO4/SDI1 [PC7] SDO5/SDI0 [PC6] VCCSS (3) GNDS (3) INTERRUPT AND MODE CONTROL MODA/IRQA MODB/IRQB MODD/IRQD RESET PLL AND CLOCK PINIT/NMI PCAP VCCP GNDP EXTAL SERIAL HOST INTERFACE (SHI) MOSI/HA0 SS/HA2 MISO/SDA SCK/SCL HREQ QUIET POWER VCCHQ (4) VCCLQ (4) GNDQ (4) Figure 2-1 Signals Identified by Functional Group DSP56364 Technical Data, Rev. 4 2-2 Freescale Semiconductor Power 2.2 Power Table 2-2 Power Inputs Description PLL Power--VCCP is VCC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. There is one VCCP input. Quiet Core (Low) Power--VCCQL is an isolated power for the internal processing logic. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four VCCQL inputs. Quiet External (High) Power--VCCQH is a quiet power source for I/O lines. This input must be tied externally to all other chip power inputs. The user must provide adequate decoupling capacitors. There are four VCCQH inputs. Address Bus Power--VCCA is an isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four VCCA inputs. Data Bus Power--VCCD is an isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There is one VCCD inputs. Bus Control Power--VCCC is an isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There is one VCCC inputs. SHI and ESAI --VCCS is an isolated power for the SHI and ESAI. This input must be tied externally to all other chip power inputsL. The user must provide adequate external decoupling capacitors. There are three VCCS inputs. Power Name VCCP VCCQL (4) VCCQH (4) VCCA (4) VCCD (1) VCCC (1) VCCS (3) 2.3 Ground Table 2-3 Grounds Description PLL Ground--GNDP is ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 F capacitor located as close as possible to the chip package. There is one GNDP connection. Quiet Ground--GNDQ is an isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDQ connections. Address Bus Ground--GNDA is an isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDA connections. Data Bus Ground--GNDD is an isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There is one GNDD connections. Ground Name GNDP GNDQ (4) GNDA (4) GNDD (1) DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 2-3 Clock and PLL Table 2-3 Grounds (continued) Ground Name GNDC (1) Description Bus Control Ground--GNDC is an isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There is one GNDC connections. SHI and ESAI --GNDS is an isolated ground for the SHI and ESAI. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are three GNDS connections. GNDS (3) 2.4 Clock and PLL Table 2-4 Clock and PLL Signals Type Input State during Reset Input Signal Description External Clock Input--An external clock source must be connected to EXTAL in order to supply the clock to the internal clock generator and PLL. PLL Capacitor--PCAP is an input connecting an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to VCCP. If the PLL is not used, PCAP may be tied to VCC, GND, or left floating. Signal Name EXTAL PCAP Input Input PINIT/NMI Input Input PLL Initial/Nonmaskable Interrupt--During assertion of RESET, the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled. After RESET de assertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized to internal system clock. This input is 5 V tolerant. 2.5 External Memory Expansion Port (Port A) When the DSP56364 enters a low-power standby mode (stop or wait), it tri-states the relevant port A signals: D0-D7, AA0, AA1, RD, WR, CAS. 2.5.1 External Address Bus Table 2-5 External Address Bus Signals State during Reset Signal Name A0-A17 Type Output Signal Description Keeper active Address Bus--A0-A17 are active-high outputs that specify the address for external program and data memory accesses. Otherwise, the signals are kept to their previous values by internal weak keepers. To minimize power dissipation, A0-A17 do not change state when external memory spaces are not being accessed. DSP56364 Technical Data, Rev. 4 2-4 Freescale Semiconductor External Memory Expansion Port (Port A) 2.5.2 Signal Name D0-D7 External Data Bus Table 2-6 External Data Bus Signals Type Input/ Output State during Reset Tri-stated Signal Description Data Bus--D0-D7 are active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. D0-D7 are tri-stated during hardware reset and when the DSP is in the stop or wait low-power standby mode. 2.5.3 External Bus Control Table 2-7 External Bus Control Signals State during Reset Tri-stated Signal Name AA0-AA1/ Type Output Signal Description Address Attribute or Row Address Strobe--When defined as AA, these signals can be used as chip selects or additional address lines. When defined as RAS, these signals can be used as RAS for DRAM interface. These signals are tri-statable outputs with programmable polarity. These signals are tri-stated during hardware reset and when the DSP is in the stop or wait low-power standby mode. Column Address Strobe-- CAS is an active-low output used by DRAM to strobe the column address. This signal is tri-stated during hardware reset and when the DSP is in the stop or wait low-power standby mode. Read Enable--RD is an active-low output that is asserted to read external memory on the data bus. This signal is tri-stated during hardware reset and when the DSP is in the stop or wait low-power standby mode. Write Enable-- WR is an active-low output that is asserted to write external memory on the data bus. This signal is tri-stated during hardware reset and when the DSP is in the stop or wait low-power standby mode. RAS0-RAS1 CAS Output Tri-stated RD Output Tri-stated WR Output Tri-stated TA Input Ignored Input Transfer Acknowledge--If there is no external bus activity, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) may be added to the wait states inserted by the BCR by keeping TA deasserted. In typical operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle completes one clock period after TA is asserted synchronous to the internal system clock. The number of wait states is determined by the TA input or by the bus control register (BCR), whichever is longer. The BCR can be used to set the minimum number of wait states in external bus cycles. In order to use the TA functionality, the BCR must be programmed to at least one wait state. A zero wait state access cannot be extended by TA deassertion, otherwise improper operation may result. TA can operate synchronously or asynchronously, depending on the setting of the TAS bit in the operating mode register (OMR). TA functionality may not be used while performing DRAM type accesses, otherwise improper operation may result. DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 2-5 Interrupt and Mode Control 2.6 Interrupt and Mode Control The interrupt and mode control signals select the chip's operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines. Table 2-8 Interrupt and Mode Control Signal Name MODA/IRQA Type Input State during Reset Input Signal Description Mode Select A/External Interrupt Request A--MODA/IRQA is an active-low Schmitt-trigger input, internally synchronized to the internal system clock. MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, and MODD select one of 8 initial chip operating modes, latched into the OMR when the RESET signal is deasserted. If IRQA is asserted synchronous to the internal system clock, multiple processors can be re synchronized using the WAIT instruction and asserting IRQA to exit the wait state. If the processor is in the stop standby state and IRQA is asserted, the processor will exit the stop state. This input is 5 V tolerant. MODB/IRQB Input Input Mode Select B/External Interrupt Request B--MODB/IRQB is an active-low Schmitt-trigger input, internally synchronized to the internal system clock. MODB/IRQB selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, and MODD select one of 8 initial chip operating modes, latched into OMR when the RESET signal is deasserted. If IRQB is asserted synchronous to the internal system clock, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQB to exit the wait state. This input is 5 V tolerant. MODD/IRQD Input Input Mode Select D/External Interrupt Request D--MODD/IRQD is an active-low Schmitt-trigger input, internally synchronized to the internal system clock. MODD/IRQD selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, and MODD select one of 8 initial chip operating modes, latched into OMR when the RESET signal is deasserted. If IRQD is asserted synchronous to the internal system clock, multiple processors can be re synchronized using the WAIT instruction and asserting IRQD to exit the wait state. This input is 5 V tolerant. RESET Input Input Reset--RESET is an active-low, Schmitt-trigger input. When asserted, the chip is placed in the reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, and MODD inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be supplied before deassertionof RESET. This input is 5 V tolerant. DSP56364 Technical Data, Rev. 4 2-6 Freescale Semiconductor Serial Host Interface 2.7 Serial Host Interface Table 2-9 Serial Host Interface Signals The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode. Signal Name SCK Signal Type Input or output State during Reset Tri-stated Signal Description SPI Serial Clock--The SCK signal is an output when the SPI is configured as a master and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the slave select (SS) signal is not asserted. In both the master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI transfer protocol. I2C Serial Clock--SCL carries the clock for I2C bus transactions in the I2C mode. SCL is a Schmitt-trigger input when configured as a slave and an open-drain output when configured as a master. SCL should be connected to VCC through a pull-up resistor. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant. SCL Input or output Tri-stated MISO Input or output Tri-stated SPI Master-In-Slave-Out--When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave mode when SS is deasserted. An external pull-up resistor is not required for SPI operation. I2C Data and Acknowledge--In I2C mode, SDA is a Schmitt-trigger input when receiving and an open-drain output when transmitting. SDA should be connected to VCC through a pull-up resistor. SDA carries the data for I2C transactions. The data in SDA must be stable during the high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of start and stop events. A high-to-low transition of the SDA line while SCL is high is a unique situation, and is defined as the start event. A low-to-high transition of SDA while SCL is high is a unique situation defined as the stop event. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant. SDA Input or open-drain output Tri-stated MOSI Input or output Tri-stated SPI Master-Out-Slave-In--When the SPI is configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for the SPI Slave mode. DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 2-7 Serial Host Interface Table 2-9 Serial Host Interface Signals (continued) Signal Name HA0 Signal Type Input State during Reset Tri-stated Signal Description I2C Slave Address 0--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for I2C slave mode, the HA0 signal is used to form the slave device address. HA0 is ignored when configured for the I2C master mode. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant. SS Input Input SPI Slave Select--This signal is an active low Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI master mode, this signal should be kept deasserted (pulled high). If it is asserted while configured as SPI master, a bus error condition is flagged. If SS is deasserted, the SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance state. I2C Slave Address 2--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for the I2C Slave mode, the HA2 signal is used to form the slave device address. HA2 is ignored in the I2C master mode. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 5 V tolerant. HREQ Input or Output Tri-stated Host Request--This signal is an active low Schmitt-trigger input when configured for the master mode but an active low output when configured for the slave mode. When configured for the slave mode, HREQ is asserted to indicate that the SHI is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer. When configured for the master mode, HREQ is an input. When asserted by the external slave device, it will trigger the start of the data word transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ to proceed to the next transfer. This signal is tri-stated during hardware, software, personal reset, or when the HREQ1-HREQ0 bits in the HCSR are cleared. There is no need for external pull-up in this state. This input is 5 V tolerant. HA2 Input Input DSP56364 Technical Data, Rev. 4 2-8 Freescale Semiconductor Enhanced Serial Audio Interface 2.8 Signal Name HCKR Enhanced Serial Audio Interface Table 2-10 Enhanced Serial Audio Interface Signals Signal Type Input or output State during Reset GPIO disconnected Signal Description High Frequency Clock for Receiver--When programmed as an input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [DACs]) or as an additional system clock. Port C 2--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. PC2 Input, output, or disconnected GPIO disconnected HCKT Input or output GPIO disconnected High Frequency Clock for Transmitter--When programmed as an input, this signal provides a high frequency clock source for the ESAI transmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external DACs) or as an additional system clock. Port C 5--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. PC5 Input, output, or disconnected GPIO disconnected FSR Input or output GPIO disconnected Frame Sync for Receiver--This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. PC1 Input, output, or disconnected GPIO disconnected Port C 1--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. FST Input or output GPIO disconnected Frame Sync for Transmitter--This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR). DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 2-9 Enhanced Serial Audio Interface Table 2-10 Enhanced Serial Audio Interface Signals (continued) Signal Name PC4 Signal Type Input, output, or disconnected State during Reset GPIO disconnected Signal Description Port C 4--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SCKR Input or output GPIO disconnected Receiver Serial Clock--SCKR provides the receiver serial bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. PC0 Input, output, or disconnected GPIO disconnected Port C 0--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SCKT Input or output GPIO disconnected Transmitter Serial Clock--This signal provides the serial bit rate clock for the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. Port C 3--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SDO5 Output GPIO disconnected GPIO disconnected GPIO disconnected Serial Data Output 5--When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0--When programmed as a receiver, SDI0 is used to receive serial data into the RX0 serial receive shift register. Port C 6--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SDO4 Output GPIO disconnected Serial Data Output 4--When programmed as a transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register. PC3 Input, output, or disconnected GPIO disconnected SDI0 Input PC6 Input, output, or disconnected DSP56364 Technical Data, Rev. 4 2-10 Freescale Semiconductor Enhanced Serial Audio Interface Table 2-10 Enhanced Serial Audio Interface Signals (continued) Signal Name SDI1 Signal Type Input State during Reset GPIO disconnected GPIO disconnected Signal Description Serial Data Input 1--When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register. Port C 7--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SDO3 Output GPIO disconnected GPIO disconnected GPIO disconnected Serial Data Output 3--When programmed as a transmitter, SDO3 is used to transmit data from the TX3 serial transmit shift register. Serial Data Input 2--When programmed as a receiver, SDI2 is used to receive serial data into the RX2 serial receive shift register. Port C 8--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SDO2 Output GPIO disconnected GPIO disconnected GPIO disconnected Serial Data Output 2--When programmed as a transmitter, SDO2 is used to transmit data from the TX2 serial transmit shift register Serial Data Input 3--When programmed as a receiver, SDI3 is used to receive serial data into the RX3 serial receive shift register. Port C 9--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SDO1 Output GPIO disconnected GPIO disconnected Serial Data Output 1--SDO1 is used to transmit data from the TX1 serial transmit shift register. Port C 10--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. SDO0 Output GPIO disconnected GPIO disconnected Serial Data Output 0--SDO0 is used to transmit data from the TX0 serial transmit shift register. Port C 11--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. PC7 Input, output, or disconnected SDI2 Input PC8 Input, output, or disconnected SDI3 Input PC9 Input, output, or disconnected PC10 Input, output, or disconnected PC11 Input, output, or disconnected DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 2-11 JTAG/OnCE Interface 2.9 Signal Name TCK JTAG/OnCE Interface Table 2-11 JTAG/OnCE Interface Signal Type Input State during Reset Input Signal Description Test Clock--TCK is a test clock input signal used to synchronize the JTAG test logic. It has an internal pull-up resistor. This input is 5 V tolerant. TDI Input Input Test Data Input--TDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 5 V tolerant. TDO Output Tri-stated Test Data Output--TDO is a test data serial output signal used for test instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. Test Mode Select--TMS is an input signal used to sequence the test controller's state machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 5 V tolerant. TMS Input Input Table 2-12 GPIO Signals Signal Name GPIO0-GP IO3 Signal Type Input, output or disconnected State during Reset Disconnected Signal Description GPIO0-3- The General Purpose I/O pins are used for control and handshake functions between the DSP and external circuitry. Each Port B GPIO pin may be individually programmed as an input, output or disconnected DSP56364 Technical Data, Rev. 4 2-12 Freescale Semiconductor 3 3.1 Specifications Introduction The DSP56364 is a high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs and outputs. The DSP56364 specifications are preliminary and are from design simulations, and may not be fully tested or guaranteed. Finalized specifications will be published after full characterization and device qualifications are complete. 3.2 Maximum Ratings CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (e.g., either GND or VCC). The suggested value for a pullup or pulldown resistor is 10 k. NOTE In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist. DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-1 Thermal Characteristics Table 3-1 Maximum Ratings Rating1 Supply Voltage All input voltages excluding "5 V tolerant" inputs3 All "5 V tolerant" input voltages3 Current drain per pin excluding VCC and GND Operating temperature range Storage temperature 1 Symbol VCC VIN VIN5 I TJ TSTG Value1, 2 Unit V V V mA -0.3 to +4.0 GND -0.3 to VCC + 0.3 GND - 0.3 to VCC + 3.95 10 -40 to +105 C C -55 to +125 2 GND = 0 V, VCC = 3.3 V 0.16 V, TJ = -0C to +105C, CL = 50 pF Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 3 CAUTION: All "5 V Tolerant" input voltages must not be more than 3.95 V greater than the supply voltage; this restriction applies to "power on", as well as during normal operation. In any case, the input voltages cannot be more than 5.75 V. "5 V Tolerant" inputs are inputs that tolerate 5 V. 3.3 Thermal Characteristics Table 3-2 Thermal Characteristics Characteristic Symbol RJA or JA RJC or JC JT TQFP Value 49.87 9.26 2.0 Unit Junction-to-ambient thermal resistance1 Junction-to-case thermal resistance2 Thermal characterization parameter 1 C/W C/W C/W Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed circuit board per SEMI G38-87 in natural convection.(SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111.) Measurements were done with parts mounted on thermal test boards conforming to specification EIA/JESD51-3. 2 Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88, with the exception that the cold plate temperature is used for the case temperature. DSP56364 Technical Data, Rev. 4 3-2 Freescale Semiconductor DC Electrical Characteristics 3.4 DC Electrical Characteristics Table 3-3 DC Electrical Characteristics1 Characteristics Symbol VCC Min 3.14 Typ 3.3 Max 3.46 Unit V V VIH VIHP VIHP VIHX 2.0 2.0 -- -- VCC VCC + 3.95 VCC + 3.95 VCC V VIL VILP VILP VILX IIN ITSI VOH 2.4 VCC - 0.01 VOL mA)4,5 -- -- -- -- 0.4 0.01 -- -- -- -- V V V -0.3 -0.3 -0.3 -0.3 -10 -10 -- -- -- -- -- -- 0.8 0.8 0.3xVCC 0.2 x VCC 10 10 A A Supply voltage Input high voltage * D(0:7), TA * MOD2/IRQ2, RESET, PINIT/NMI and all JTAG/ESAI/GPIO/SHI (SPI mode)pins * SHI (I2C mode) pins * EXTAL3 Input low voltage * D(0:7), TA, MOD2/IRQ2, RESET, PINIT * JTAG/ESAI/GPIO/SHI (SPI mode)pins * SHI (I2C mode) pins * EXTAL3 Input leakage current High impedance (off-state) input current (@ 2.4 V / 0.4 V) Output high voltage * TTL (IOH = -0.4 mA)4,5 1.5 0.8 x VCC -- -- * CMOS (IOH = -10 A)4 Output low voltage * TTL (IOL = 3.0 mA, open-drain pins IOL = 6.7 * CMOS (IOL = 10 A)4 Internal supply current6 at internal clock of 100Mhz * In Normal mode * In Wait mode7 * In Stop mode8 PLL supply current Input capacitance4 1 2 ICCI ICCW ICCS -- -- -- -- 127 7. 5 100 1 -- 181 11 150 2.5 10 mA mA A mA pF CIN -- VCC = 3.3 V .16 V; TJ = 0C to +105C, CL = 50 pF Refers to MODA/IRQA, MODB/IRQB, and MODD/IRQD pins 3 Driving EXTAL to the low VIHX or the high VILX value may cause additional power consumption (DC current). To minimize power consumption, the minimum VIHX should be no lower than 0.9 x VCC and the maximum VILX should be no higher than 0.1 x VCC. 4 Periodically sampled and not 100% tested DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-3 AC Electrical Characteristics 5 6 This characteristic does not apply to PCAP. Section 5, "Design Considerations" provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCC = 3.3 V at TJ = 105C. Maximum internal supply current is measured with VCC = 3.46 V at TJ = 105C. 7 In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL signal is disabled during Stop state. 8 In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to float). 3.5 AC Electrical Characteristics The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.3 V and a VIH minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 8 of the previous table. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal's transition. DSP56364 output levels are measured with the production test machine VOL and VOH reference levels set at 0.4 V and 2.4 V, respectively. NOTE Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15 MHz and rated speed. 3.6 Internal Clocks Table 3-4 Internal Clocks Expression1, 2 Characteristics Symbol Min Typ (Ef x MF)/ (PDF x DF) Ef/2 Max -- Internal operation frequency with PLL enabled f -- Internal operation frequency with PLL disabled Internal clock high period * With PLL disabled * With PLL enabled and MF 4 f TH -- -- -- 0.49 x ETC x PDF x DF/MF 0.47 x ETC x PDF x DF/MF ETC -- -- 0.51 x ETC x PDF x DF/MF 0.53 x ETC x PDF x DF/MF * With PLL enabled and MF > 4 -- DSP56364 Technical Data, Rev. 4 3-4 Freescale Semiconductor EXTERNAL CLOCK OPERATION Table 3-4 Internal Clocks (continued) Expression1, 2 Characteristics Symbol Min Internal clock low period * With PLL disabled * With PLL enabled and MF 4 TL -- 0.49 x ETC x PDF x DF/MF 0.47 x ETC x PDF x DF/MF TC -- ETC -- -- 0.51 x ETC x PDF x DF/MF 0.53 x ETC x PDF x DF/MF -- Typ Max * With PLL enabled and MF > 4 -- Internal clock cycle time with PLL enabled ETC x PDF x DF/MF 2 x ETC TC Internal clock cycle time with PLL disabled Instruction cycle time 1 TC ICYC -- -- -- -- DF = Division Factor Ef = External frequency ETC = External clock cycle MF = Multiplication Factor PDF = Predivision Factor TC = internal clock cycle 2 See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion of the PLL. 3.7 EXTERNAL CLOCK OPERATION The DSP56364 system clock is an externally supplied square wave voltage source connected to EXTAL(See Figure 3-1). VIHC EXTAL VILC ETH 2 4 ETL 3 ETC Midpoint Note: The midpoint is 0.5 (VIHC + VILC). Figure 3-1 External Clock Timing DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-5 Phase Lock Loop (PLL) Characteristics Table 3-5 Clock Operation No. 1 Characteristics Frequency of EXTAL (EXTAL Pin Frequency) The rise and fall time of this external clock should be 3 ns maximum. 2 EXTAL input high1, 2 * With PLL disabled (46.7%-53.3% duty cycle6) * With PLL enabled (42.5%-57.5% duty cycle6) 3 EXTAL input low1, 2 * With PLL disabled (46.7%-53.3% duty cycle6) * With PLL enabled (42.5%-57.5% duty cycle6) 4 EXTAL cycle time2 * With PLL disabled * With PLL enabled 1 2 Symbol Ef Min 0 Max 100.0 ETH 4.67 ns 4.25 ns 157.0 s ETL 4.67 ns 4.25 ns 157.0 s ETC 10.00 ns 10.00 ns 273.1 s Measured at 50% of the input transition. The maximum value for PLL enabled is given for minimum VCO and maximum MF. 3.8 Phase Lock Loop (PLL) Characteristics Table 3-6 PLL Characteristics Characteristics Min 30 Max 200 Unit MHz pF (MF x 580) - 100 MF x 830 (MF x 780) - 140 MF x 1470 VCO frequency when PLL enabled (MF x Ef x 2/PDF) PLL external capacitor (PCAP pin to VCCP) (CPCAP1) * @ MF 4 * @ MF > 4 1 CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). The recommended value in pF for CPCAP can be computed from one of the following equations: (MF x 680)-120, for MF 4, or MF x 1100, for MF > 4. DSP56364 Technical Data, Rev. 4 3-6 Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing 3.9 No. 8 9 Reset, Stop, Mode Select, and Interrupt Timing Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1 Characteristics Delay from RESET assertion to all pins at reset value3 Required RESET duration4 * Power on, external clock generator, PLL disabled * Power on, external clock generator, PLL enabled * Power on, internal oscillator * During STOP, XTAL disabled (PCTL Bit 16 = 0) * During STOP, XTAL enabled (PCTL Bit 16 = 1) * During normal operation 50 x ETC 1000 x ETC 75000 x ETC 75000 x ETC 2.5 x TC 2.5 x TC 500.0 10.0 0.75 0.75 25.0 25.0 -- -- -- -- -- -- ns ns s ms ms ns Expression2 -- Min -- Max 26.0 Unit ns 10 Delay from asynchronous RESET deassertion to first external address output (internal reset deassertion)5 * Minimum * Maximum 3.25 x TC + 2.0 20.25 TC + 7.50 34.5 -- 30.0 0.0 6.6 6.6 -- 211.5 -- -- -- -- ns ns ns ns ns ns 13 14 15 16 17 Mode select setup time Mode select hold time Minimum edge-triggered interrupt request assertion width Minimum edge-triggered interrupt request deassertion width Delay from IRQA, IRQB, IRQD, NMI assertion to external memory access address out valid * Caused by first interrupt instruction fetch * Caused by first interrupt instruction execution 4.25 x TC + 2.0 7.25 x TC + 2.0 10 x TC + 5.0 44.5 74.5 105.0 -- -- -- ns ns ns 18 Delay from IRQA, IRQB, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution Delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts 6, 7 Delay from RD assertion to interrupt request deassertion for level sensitive fast interrupts6, 7 19 3.75 x TC + WS x TC - 10.94 -- -- ns 20 3.25 x TC + WS x TC - 10.94 -- -- ns DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-7 Reset, Stop, Mode Select, and Interrupt Timing Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1 (continued) No. 21 Characteristics Delay from WR assertion to interrupt request deassertion for level sensitive fast interrupts6, 7 * DRAM for all WS * SRAM WS = 1 * SRAM WS = 2, 3 * SRAM WS 4 24 25 Duration for IRQA assertion to recover from Stop state Delay from IRQA assertion to fetch of first instruction (when exiting Stop)3, 8 * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) * PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop Delay) 26 Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)3, 8 * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) * PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay) 27 Interrupt Requests Rate * ESAI, SCI * DMA * IRQ, NMI (edge trigger) * IRQ, NMI (level trigger) 28 DMA Requests Rate * Data read from ESAI, SCI * Data write to ESAI, SCI * IRQ, NMI (edge trigger) 6TC 7TC 3TC -- -- -- 60.0 70.0 30.0 ns ns ns 12TC 8TC 8TC 12TC -- -- -- -- 120.0 80.0 80.0 120.0 ns ns ns ns PLC x ETC x PDF + (128K - PLC/2) x TC PLC x ETC x PDF + (20.5 0.5) x TC 5.5 x TC 13.6 -- ms PLC x ETC x PDF + (128 K - PLC/2) x TC PLC x ETC x PDF + (23.75 0.5) x TC (8.25 0.5) x TC 1.3 13.6 ms (WS + 3.5) x TC - 10.94 (WS + 3.5) x TC - 10.94 (WS + 3) x TC - 10.94 (WS + 2.5) x TC - 10.94 -- -- -- -- 5.9 -- -- -- -- -- Expression2 Min Max Unit ns 232.5 ns 77.5 12.3 ms 87.5 ns 12.3 -- ms 55.0 -- ns DSP56364 Technical Data, Rev. 4 3-8 Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1 (continued) No. 29 1 2 Characteristics Delay from IRQA, IRQB, IRQD, NMI assertion to external memory (DMA source) access address out valid Expression2 4.25 x TC + 2.0 Min 44.0 Max -- Unit ns VCC = 3.3 V 0.16 V; TJ = 0C to + 105C, CL = 50 pF Use expression to compute maximum value. 3 Periodically sampled and not 100% tested 4 For an external clock generator, RESET duration is measured during the time in which RESET is asserted, VCC is valid, and the EXTAL input is active and valid. For internal oscillator, RESET duration is measured during the time in which RESET is asserted and VCC is valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. When the VCC is valid, but the other "required RESET duration" conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. 5 For an external clock generator, RESET duration is measured during the time in which RESET is asserted, V CC is valid, and the EXTAL input is active and valid. For internal oscillator, RESET duration is measured during the time in which RESET is asserted and VCC is valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. When the VCC is valid, but the other "required RESET duration" conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. 6 When using fast interrupts and IRQA, IRQB, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. 7 WS = number of wait states (measured in clock cycles, number of T ) C 8 This timing depends on several settings: For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL Bit 17 = 0), a stabilization delay is required to assure the oscillator is stable before executing programs. In that case, resetting the Stop delay (OMR Bit 6 = 0) will provide the proper delay. While it is possible to set OMR Bit 6 = 1, it is not recommended and these specifications do not guarantee timings for that case. For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization delay is required and recovery time will be minimal (OMR Bit 6 setting is ignored). For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined by the PCTL Bit 17 and OMR Bit 6 settings. For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery will end when the last of these two events occurs. The stop delay counter completes count or PLL lock procedure completion. PLC value for PLL disable is 0. The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency (i.e., for 100 MHz it is 4096/100 MHz = 40 s). During the stabilization period, TC, TH, and TL will not be constant, and their width may vary, so timing may vary as well. 9. If PLL does not lose lock. DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-9 Reset, Stop, Mode Select, and Interrupt Timing VIH RESET 9 8 All Pins Reset Value 10 A0-A17 First Fetch AA0460 Figure 3-2 Reset Timing First Interrupt Instruction A0-A17 Execution/Fetch RD 20 WR 21 IRQA, IRQB, IRQD, NMI 17 19 a) First Interrupt Instruction Execution General Purpose I/O 18 IRQA, IRQB, IRQD, NMI b) General Purpose I/O AA0462 Figure 3-3 External Fast Interrupt Timing DSP56364 Technical Data, Rev. 4 3-10 Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing IRQA, IRQB, IRQD, NMI 15 IRQA, IRQB, IRQD, NMI 16 AA0463 Figure 3-4 External Interrupt Timing (Negative Edge-Triggered) RESET 13 14 MODA, MODB,MODD, PINIT VIH VIL VIH VIL VIH IRQA, IRQB, IRQD, NMI AA0465 Figure 3-5 Operating Mode Select Timing 24 IRQA 25 A0-A17 First Instruction Fetch AA0466 Figure 3-6 Recovery from Stop State Using IRQA DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-11 External Memory Expansion Port (Port A) IRQA 26 25 A0-A17 First IRQA Interrupt Instruction Fetch AA0467 Figure 3-7 Recovery from Stop State Using IRQA Interrupt Service A0-A17 DMA Source Address RD WR IRQA, IRQB, IRQD, NMI 29 First Interrupt Instruction Execution AA1104 Figure 3-8 External Memory Access (DMA Source) Timing 3.10 3.10.1 No. 100 External Memory Expansion Port (Port A) SRAM Timing Table 3-8 SRAM Read and Write Accesses1 Characteristics Address valid and AA assertion pulse width Symbol tRC, tWC Expression2 (WS + 1) x TC - 4.0 [1 WS 3] (WS + 2) x TC - 4.0 [4 WS 7] (WS + 3) x TC - 4.0 [WS 8] 106.0 -- ns 56.0 -- ns Min 16.0 Max -- Unit ns DSP56364 Technical Data, Rev. 4 3-12 Freescale Semiconductor External Memory Expansion Port (Port A) Table 3-8 SRAM Read and Write Accesses1 (continued) No. 101 Characteristics Address and AA valid to WR assertion Symbol tAS Expression2 0.25 x TC - 2.0 [WS = 1] 0.75 x TC - 2.0 [2 WS 3] 1.25 x TC - 2.0 [WS 4] 102 WR assertion pulse width tWP 1.5 x TC - 4.0 [WS = 1] All frequencies: WS x TC - 4.0 [2 WS 3] (WS - 0.5) x TC - 4.0 [WS 4] 103 WR deassertion to address not valid tWR 0.25 x TC - 2.0 [1 WS 3] 1.25 x TC - 2.0 [4 WS 7] 2.25 x TC - 2.0 [WS 8] All frequencies: 1.25 x TC - 4.0 [4 WS 7] 2.25 x TC - 4.0 [WS 8] 104 Address and AA valid to input data valid tAA, tAC (WS + 0.75) x TC - 7.0 [WS 1] 105 RD assertion to input data valid tOE (WS + 0.25) x TC - 7.0 [WS 1] 106 107 RD deassertion to data not valid (data hold time) Address valid to WR deassertion3 tOHZ tAW (WS + 0.75) x TC - 4.0 [WS 1] 0.0 13.5 -- -- ns ns -- 5.5 ns -- 10.5 ns 18.5 -- ns 8.5 -- ns 20.5 -- ns 10.5 -- ns 0.5 -- ns 31.0 -- ns 16.0 -- ns 11.0 -- ns 10.5 -- ns 5.5 -- ns Min 0.5 Max -- Unit ns DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-13 External Memory Expansion Port (Port A) Table 3-8 SRAM Read and Write Accesses1 (continued) No. 108 Characteristics Data valid to WR deassertion (data setup time) Symbol tDS (tDW) Expression2 (WS - 0.25) x TC - 3.0 [WS 1] 109 Data hold time from WR deassertion tDH 0.25 x TC - 2.0 [1 WS 3] 1.25 x TC - 2.0 [4 WS 7] 2.25 x TC - 2.0 [WS 8] 113 RD deassertion time 0.75 x TC - 4.0 [1 WS 3] 1.75 x TC - 4.0 [4 WS 7] 2.75 x TC - 4.0 [WS 8] 114 WR deassertion time 0.5 x TC - 4.0 [WS = 1] TC - 2.0 [2 WS 3] 2.5 x TC - 4.0 [4 WS 7] 3.5 x TC - 4.0 [WS 8] 115 116 117 Address valid to RD assertion RD assertion pulse width RD deassertion to address not valid 0.5 x TC - 4.0 (WS + 0.25) x TC -4.0 0.25 x TC - 2.0 [1 WS 3] 1.25 x TC - 2.0 [4 WS 7] 2.25 x TC - 2.0 [WS 8] 20.5 -- ns 10.5 -- ns 1.0 8.5 0.5 -- -- -- ns ns ns 31.0 -- ns 21.0 -- ns 6.0 -- ns 1.0 -- ns 23.5 -- ns 13.5 -- ns 3.5 -- ns 20.5 -- ns 10.5 -- ns 0.5 -- ns Min 4.5 Max -- Unit ns DSP56364 Technical Data, Rev. 4 3-14 Freescale Semiconductor External Memory Expansion Port (Port A) Table 3-8 SRAM Read and Write Accesses1 (continued) No. 118 119 1 2 Characteristics TA setup before RD or WR deassertion4 TA hold after RD or WR deassertion Symbol Expression2 0.25 x TC + 2.0 Min 4.5 0 Max -- -- Unit ns ns All timings for 100 MHz are measured from 0.5 * Vcc to .05 * Vcc WS is the number of wait states specified in the BCR. 3 Timings 100, 107 are guaranteed by design, not tested. 4 In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to remain active. 100 A0-A17 AA0-AA1 113 RD 115 WR 104 119 TA D0-D7 Data In AA0468 118 105 106 116 117 Figure 3-9 SRAM Read Access DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-15 External Memory Expansion Port (Port A) 100 A0-A17 AA0-AA3 107 101 WR 114 RD 119 TA 108 110 112 D0-D23 Data Out AA0469 109 111 118 102 103 Figure 3-10 SRAM Write Access 3.10.2 DRAM Timing The selection guides provided in Figure 3-11 and Figure 3-14 should be used for primary selection only. Final selection should be based on the timing provided in the following tables. As an example, the selection guide suggests that 4 wait states must be used for 100 MHz operation when using Page Mode DRAM. However, by using the information in the appropriate table, a designer may choose to evaluate whether fewer wait states might be used by determining which timing prevents operation at 100 MHz, running the chip at a slightly lower frequency (e.g., 95 MHz), using faster DRAM (if it becomes available), and control factors such as capacitive and resistive load to improve overall system performance. DSP56364 Technical Data, Rev. 4 3-16 Freescale Semiconductor External Memory Expansion Port (Port A) DRAM Type (tRAC ns) Note: This figure should be use for primary selection. For exact and detailed timings see the following tables. 100 80 70 60 50 40 66 80 100 120 Chip Frequency (MHz) 1 Wait States 2 Wait States 3 Wait States 4 Wait States AA0472 Figure 3-11 DRAM Page Mode Wait States Selection Guide Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3 20 MHz4 No. Characteristics Symbol Expression Min 131 Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses 132 133 CAS assertion to data valid (read) Column address valid to data valid (read) tCAC tAA tPC 2 x TC 100.0 Max -- Min 66.7 Max -- ns 30 MHz4 Unit 1.25 x TC TC - 7.5 1.5 x TC - 7.5 62.5 -- 41.7 -- -- -- 42.5 67.5 -- -- 25.8 42.5 ns ns DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-17 External Memory Expansion Port (Port A) Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3 (continued) 20 MHz4 No. Characteristics Symbol Expression Min 134 CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion CAS assertion pulse width Last CAS deassertion to RAS deassertion5 BRW[1:0] = 00 * BRW[1:0] = 01 * BRW[1:0] = 10 * BRW[1:0] = 11 139 140 CAS deassertion pulse width Column address valid to CAS assertion CAS assertion to column address not valid Last column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion CAS assertion to WR deassertion WR assertion pulse width Last WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (Write) CAS assertion to data not valid (write) WR assertion to CAS assertion tCP tASC 3.25 x TC - 6.0 4.25 x TC - 6.0 6.25 x TC - 6.0 0.5 x TC - 4.0 0.5 x TC - 4.0 0.75 x TC - 4.0 2 x TC - 4.0 0.75 x TC - 3.8 0.25 x TC - 3.7 0.5 x TC - 4.2 1.5 x TC - 4.5 1.75 x TC - 4.3 1.75 x TC - 4.3 0.25 x TC - 4.0 0.75 x TC - 4.0 TC - 4.3 156.5 206.5 306.5 21.0 21.0 -- -- -- 102.2 135.5 202.1 12.7 12.7 -- -- -- -- -- ns ns ns ns ns tOFF 0.75 x TC - 4.0 2 x TC - 4.0 0.75 x TC - 4.0 1.75 x TC - 6.0 0.0 Max -- Min 0.0 Max -- ns 30 MHz4 Unit 135 tRSH 33.5 -- 21.0 -- ns 136 tRHCP 96.0 -- 62.7 -- ns 137 138 tCAS tCRP 33.5 81.5 -- -- 21.0 52.3 -- -- ns ns 141 tCAH 33.5 -- 21.0 -- ns 142 tRAL 96.0 -- 62.7 -- ns 143 144 145 146 147 148 149 150 151 tRCS tRCH tWCH tWP tRWL tCWL tDS tDH tWCS 33.7 8.8 20.8 70.5 83.2 83.2 8.5 33.5 45.7 -- -- -- -- -- -- -- -- -- 21.2 4.6 12.5 45.5 54.0 54.0 4.3 21.0 29.0 -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns DSP56364 Technical Data, Rev. 4 3-18 Freescale Semiconductor External Memory Expansion Port (Port A) Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3 (continued) 20 MHz4 No. Characteristics Symbol Expression Min 152 153 154 155 156 1 2 3 4 5 6 30 MHz4 Unit Min 46.0 -- 0.0 24.7 -- Max -- 25.8 -- -- 8.3 ns ns ns ns ns Max -- 42.5 -- -- 12.5 Last RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid 6 WR assertion to data active WR deassertion to data high impedance tROH tGA tGZ 1.5 x TC - 4.0 TC - 7.5 71.0 -- 0.0 0.75 x TC - 0.3 0.25 x TC 37.2 -- The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 2 x TC for read-after-read or write-after-write sequences). Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state (See Figure 3-14.). BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-19 External Memory Expansion Port (Port A) Table 3-10 DRAM Page Mode Timings, Two Wait States1, 2, 3, 4 66 MHz No. Characteristics Symbol Expression5 Min 131 Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses 132 CAS assertion to data valid (read) tCAC tPC 2 x TC 1.25 x TC 1.5 x TC - 7.5 1.5 x TC - 6.5 133 Column address valid to data valid (read) tAA 2.5 x TC - 7.5 2.5 x TC - 6.5 134 CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion CAS assertion pulse width Last CAS deassertion to RAS deassertion6 * BRW[1:0] = 00 * BRW[1:0] = 01 * BRW[1:0] = 10 * BRW[1:0] = 11 139 140 141 142 CAS deassertion pulse width Column address valid to CAS assertion CAS assertion to column address not valid Last column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion CAS assertion to WR deassertion WR assertion pulse width tCP tASC tCAH tRAL tCRP 2.0 x TC - 6.0 3.5 x TC - 6.0 4.5 x TC - 6.0 6.5 x TC - 6.0 1.25 x TC - 4.0 TC - 4.0 1.75 x TC - 4.0 3 x TC - 4.0 1.25 x TC - 3.8 0.5 x TC - 3.7 1.5 x TC - 4.2 2.5 x TC - 4.5 24.4 47.2 62.4 92.8 14.9 11.2 22.5 41.5 -- -- -- -- -- -- -- -- 19.0 37.8 50.3 75.3 11.6 8.5 17.9 33.5 -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns tOFF 1.75 x TC - 4.0 3.25 x TC - 4.0 1.5 x TC - 4.0 45.4 Max -- Min 37.5 Max -- ns 80 MHz Unit 41.1 -- 34.4 -- ns -- -- -- -- 0.0 15.2 -- 30.4 -- -- -- -- -- -- 0.0 -- 12.3 -- 24.8 -- ns ns ns ns ns 135 136 tRSH tRHCP 22.5 45.2 -- -- 17.9 36.6 -- -- ns ns 137 138 tCAS 18.7 -- 14.8 -- ns 143 144 145 146 tRCS tRCH tWCH tWP 15.1 3.9 18.5 33.5 -- -- -- -- 11.8 2.6 14.6 26.8 -- -- -- -- ns ns ns ns DSP56364 Technical Data, Rev. 4 3-20 Freescale Semiconductor External Memory Expansion Port (Port A) Table 3-10 DRAM Page Mode Timings, Two Wait States1, 2, 3, 4 (continued) 66 MHz No. Characteristics Symbol Expression5 Min 147 148 149 Last WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) tRWL tCWL tDS 2.75 x TC - 4.3 2.5 x TC - 4.3 0.25 x TC - 3.7 0.25 x TC - 3.0 150 151 152 153 CAS assertion to data not valid (write) WR assertion to CAS assertion Last RD assertion to RAS deassertion RD assertion to data valid tDH tWCS tROH tGA 1.75 x TC - 4.0 TC - 4.3 2.5 x TC - 4.0 1.75 x TC - 7.5 1.75 x TC - 6.5 154 155 156 1 2 3 4 5 6 7 80 MHz Unit Min 26.8 27.0 -- 0.1 17.9 8.2 27.3 -- -- 0.0 9.1 -- Max -- -- -- -- -- -- -- -- 15.4 -- -- 3.1 ns ns ns ns ns ns ns ns ns ns ns ns Max -- -- -- -- -- -- -- 19.0 -- -- -- 3.8 33.4 33.6 0.1 -- 22.5 10.9 33.9 -- -- 0.0 RD deassertion to data not valid7 WR assertion to data active WR deassertion to data high impedance tGZ 0.75 x TC - 0.3 0.25 x TC 11.1 -- The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56364. There are no DRAMs fast enough to fit to two wait states Page mode @ 100MHz (See Figure 3-11) All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 3 x TC for read-after-read or write-after-write sequences). BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-21 External Memory Expansion Port (Port A) Table 3-11 DRAM Page Mode Timings, Three Wait States1, 2, 3 No. 131 Characteristics Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses 132 133 134 135 136 137 138 CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion CAS assertion pulse width Last CAS deassertion to RAS assertion5 * BRW[1:0] = 00 * BRW[1:0] = 01 * BRW[1:0] = 10 * BRW[1:0] = 11 139 140 141 142 143 144 145 146 147 148 149 150 151 CAS deassertion pulse width Column address valid to CAS assertion CAS assertion to column address not valid Last column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion CAS assertion to WR deassertion WR assertion pulse width Last WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) WR assertion to CAS assertion tCP tASC tCAH tRAL tRCS tRCH tWCH tWP tRWL tCWL tDS tDH tWCS tCRP 2.25 x TC - 6.0 3.75 x TC - 6.0 4.75 x TC - 6.0 6.75 x TC - 6.0 1.5 x TC - 4.0 TC - 4.0 2.5 x TC - 4.0 4 x TC - 4.0 1.25 x TC - 4.0 0.75 x TC - 4.0 2.25 x TC - 4.2 3.5 x TC - 4.5 3.75 x TC - 4.3 3.25 x TC - 4.3 0.5 x TC - 4.0 2.5 x TC - 4.0 1.25 x TC - 4.3 -- -- 41.5 61.5 11.0 6.0 21.0 36.0 8.5 3.5 18.3 30.5 33.2 28.2 1.0 21.0 8.2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCAC tAA tOFF tRSH tRHCP tCAS 2.5 x TC - 4.0 4.5 x TC - 4.0 2 x TC - 4.0 Symbol tPC Expression4 2 x TC 1.25 x TC 2 x TC - 7.0 3 x TC - 7.0 Min 40.0 35.0 -- -- 0.0 21.0 41.0 16.0 Max -- -- 13.0 23.0 -- -- -- -- ns ns ns ns ns ns Unit ns DSP56364 Technical Data, Rev. 4 3-22 Freescale Semiconductor External Memory Expansion Port (Port A) Table 3-11 DRAM Page Mode Timings, Three Wait States1, 2, 3 (continued) No. 152 153 154 155 156 1 2 3 4 5 6 Characteristics Last RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid6 WR assertion to data active WR deassertion to data high impedance Symbol tROH tGA tGZ Expression4 3.5 x TC - 4.0 2.5 x TC - 7.0 Min 31.0 -- 0.0 Max -- 18.0 -- -- 2.5 Unit ns ns ns ns ns 0.75 x TC - 0.3 0.25 x TC 7.2 -- The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56364. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 4 TC for read-after-read or write-after-write sequences). BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Table 3-12 DRAM Page Mode Timings, Four Wait States1, 2, 3 No. 131 Characteristics Page mode cycle time for two consecutive accesses of the same direction. Page mode cycle time for mixed (read and write) accesses. 132 133 134 135 136 137 138 CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion CAS assertion pulse width Last CAS deassertion to RAS assertion5 * BRW[1:0] = 00 * BRW[1:0] = 01 * BRW[1:0] = 10 * BRW[1:0] = 11 139 CAS deassertion pulse width tCP tCRP 2.75 x TC - 6.0 4.25 x TC - 6.0 5.25 x TC - 6.0 7.25 x TC - 6.0 2 x TC - 4.0 -- -- 46.5 66.5 16.0 -- -- -- -- -- ns ns ns ns ns tCAC tAA tOFF tRSH tRHCP tCAS 3.5 x TC - 4.0 6 x TC - 4.0 2.5 x TC - 4.0 Symbol tPC Expression4 2 x TC 1.25 x TC 2.75 x TC - 7.0 3.75 x TC - 7.0 Min 50.0 45.0 -- -- 0.0 31.0 56.0 21.0 Max -- -- 20.5 30.5 -- -- -- -- Unit ns ns ns ns ns ns ns ns DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-23 External Memory Expansion Port (Port A) Table 3-12 DRAM Page Mode Timings, Four Wait States1, 2, 3 (continued) No. 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 1 2 3 4 5 6 Characteristics Column address valid to CAS assertion CAS assertion to column address not valid Last column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion CAS assertion to WR deassertion WR assertion pulse width Last WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) WR assertion to CAS assertion Last RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid6 WR assertion to data active WR deassertion to data high impedance Symbol tASC tCAH tRAL tRCS tRCH tWCH tWP tRWL tCWL tDS tDH tWCS tROH tGA tGZ Expression4 TC - 4.0 3.5 x TC - 4.0 5 x TC - 4.0 1.25 x TC - 4.0 1.25 x TC - 4.0 3.25 x TC - 4.2 4.5 x TC - 4.5 4.75 x TC - 4.3 3.75 x TC - 4.3 0.5 x TC - 4.0 3.5 x TC - 4.0 1.25 x TC - 4.3 4.5 x TC - 4.0 3.25 x TC - 7.0 Min 6.0 31.0 46.0 8.5 8.5 28.3 40.5 43.2 33.2 1.0 31.0 8.2 41.0 -- 0.0 Max -- -- -- -- -- -- -- -- -- -- -- -- -- 25.5 -- -- 2.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.75 x TC - 0.3 0.25 x TC 7.2 -- The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56364. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 3 x TC for read-after-read or write-after-write sequences). BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. DSP56364 Technical Data, Rev. 4 3-24 Freescale Semiconductor External Memory Expansion Port (Port A) RAS 136 131 CAS 137 140 141 A0-A17 Row Add Column Address 151 145 Column Address 144 142 Last Column Address 143 147 139 138 135 WR 146 RD 155 150 149 D0-D7 Data Out Data Out Data Out AA0473 156 148 Figure 3-12 DRAM Page Mode Write Accesses DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-25 External Memory Expansion Port (Port A) RAS 136 131 CAS 137 140 Row Add Column Address 143 WR 132 133 153 RD 134 154 D0-D7 Data In Data In Data In AA0474 152 139 141 Column Address 138 142 Last Column Address 135 A0-A17 Figure 3-13 DRAM Page Mode Read Accesses DSP56364 Technical Data, Rev. 4 3-26 Freescale Semiconductor External Memory Expansion Port (Port A) DRAM Type (tRAC ns) Note: This figure should be use for primary selection. For exact and detailed timings see the following tables. 100 80 70 60 50 40 66 80 100 120 11 Wait States 15 Wait States Chip Frequency (MHz) 4 Wait States 8 Wait States AA0475 Figure 3-14 DRAM Out-of-Page Wait States Selection Guide Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 20 MHz4 No. Characteristics3 Symbol Expression Min 157 158 159 160 Random read or write cycle time RAS assertion to data valid (read) CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion RAS assertion pulse width CAS assertion to RAS deassertion tRC tRAC tCAC tAA 5 x TC 2.75 x TC - 7.5 1.25 x TC - 7.5 1.5 x TC - 7.5 250.0 -- -- -- Max -- 130.0 55.0 67.5 Min 166.7 -- -- -- Max -- 84.2 34.2 42.5 ns ns ns ns 30 MHz4 Unit 161 tOFF 1.75 x TC - 4.0 3.25 x TC - 4.0 1.75 x TC - 4.0 0.0 -- 0.0 -- ns 162 163 164 tRP tRAS tRSH 83.5 158.5 83.5 -- -- -- 54.3 104.3 54.3 -- -- -- ns ns ns DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-27 External Memory Expansion Port (Port A) Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (continued) 20 MHz4 No. Characteristics 3 30 MHz4 Unit Min 87.7 37.7 48.0 39.7 71.0 54.3 54.3 37.7 4.3 Max -- -- 52.0 43.7 -- -- -- -- -- ns ns ns ns ns ns ns ns ns Symbol Expression Min Max -- -- 77.0 64.5 -- -- -- -- -- 2.75 x TC - 4.0 1.25 x TC - 4.0 1.5 x TC 2 1.25 x TC 2 2.25 x TC - 4.0 1.75 x TC - 4.0 1.75 x TC - 4.0 1.25 x TC - 4.0 0.25 x TC - 4.0 1.75 x TC - 4.0 3.25 x TC - 4.0 2 x TC - 4.0 1.5 x TC - 3.8 0.75 x TC - 3.7 0.25 x TC - 3.7 1.5 x TC - 4.2 3 x TC - 4.2 4.5 x TC - 4.5 4.75 x TC - 4.3 4.25 x TC - 4.3 2.25 x TC - 4.0 1.75 x TC - 4.0 3.25 x TC - 4.0 165 166 167 168 169 170 171 172 173 RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion CAS deassertion pulse width Row address valid to RAS assertion RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion RAS deassertion to WR assertion CAS assertion to WR deassertion RAS assertion to WR deassertion WR assertion pulse width WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) RAS assertion to data not valid (write) tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC 133.5 58.5 73.0 60.5 108.5 83.5 83.5 58.5 8.5 174 tCAH 83.5 -- 54.3 -- ns 175 tAR 158.5 -- 104.3 -- ns 176 tRAL 96.0 -- 62.7 -- ns 177 178 179 180 181 182 183 184 185 186 187 tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR 71.2 33.8 8.8 70.8 145.8 220.5 233.2 208.2 108.5 83.5 158.5 -- -- -- -- -- -- -- -- -- -- -- 46.2 21.3 4.6 45.8 95.8 145.5 154.0 137.4 71.0 54.3 104.3 -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns DSP56364 Technical Data, Rev. 4 3-28 Freescale Semiconductor External Memory Expansion Port (Port A) Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (continued) 20 MHz4 No. Characteristics 3 30 MHz4 Unit Min 95.7 12.7 Max -- -- ns ns Symbol Expression Min Max -- -- 3 x TC - 4.3 0.5 x TC - 4.0 1.25 x TC - 4.0 4.5 x TC - 4.0 4 x TC - 7.5 188 189 WR assertion to CAS assertion CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid3 WR assertion to data active WR deassertion to data high impedance tWCS tCSR 145.7 21.0 190 tRPC 58.5 -- 37.7 -- ns 191 192 193 194 195 1 2 tROH tGA tGZ 221.0 -- 0.0 -- 192.5 -- -- 12.5 146.0 -- 0.0 24.7 -- -- 125.8 -- -- 8.3 ns ns ns ns ns 0.75 x TC - 0.3 0.25 x TC 37.2 -- The number of wait states for out of page access is specified in the DCR. The refresh period is specified in the DCR. 3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t OFF and not tGZ. 4 Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (See Figure 3-17). Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 66 MHz No. Characteristics3 Symbol Expression4 Min 157 158 Random read or write cycle time RAS assertion to data valid (read) tRC tRAC 9 x TC 4.75 x TC - 7.5 4.75 x TC - 6.5 159 CAS assertion to data valid (read) tCAC 2.25 x TC - 7.5 2.25 x TC - 6.5 160 Column address valid to data valid (read) tAA 3 x TC - 7.5 3 x TC - 6.5 tOFF 3.25 x TC - 4.0 5.75 x TC - 4.0 136.4 -- -- -- -- -- -- 0.0 Max -- 64.5 -- 26.6 -- 40.0 -- -- Min 112.5 -- -- -- -- -- -- 0.0 Max -- -- 52.9 -- 21.6 -- 31.0 -- ns ns ns ns ns ns ns ns 80 MHz Unit 161 CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion RAS assertion pulse width 162 163 tRP tRAS 45.2 83.1 -- -- 36.6 67.9 -- -- ns ns DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-29 External Memory Expansion Port (Port A) Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 (continued) 66 MHz No. Characteristics3 Symbol Expression4 Min 164 165 166 167 168 169 170 171 172 173 CAS assertion to RAS deassertion RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion CAS deassertion pulse width Row address valid to RAS assertion RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR5 assertion RAS deassertion to WR5 assertion tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC 3.25 x TC - 4.0 4.75 x TC - 4.0 2.25 x TC - 4.0 2.5 x TC 2 1.75 x TC 2 4.25 x TC - 4.0 2.75 x TC - 4.0 3.25 x TC - 4.0 1.75 x TC - 4.0 0.75 x TC - 4.0 3.25 x TC - 4.0 5.75 x TC - 4.0 4 x TC - 4.0 2 x TC - 3.8 1.25 x TC - 3.7 0.25 x TC - 3.7 0.25 x TC - 3.0 180 181 182 183 184 185 CAS assertion to WR deassertion RAS assertion to WR deassertion WR assertion pulse width WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) tWCH tWCR tWP tRWL tCWL tDS 3 x TC - 4.2 5.5 x TC - 4.2 8.5 x TC - 4.5 8.75 x TC - 4.3 7.75 x TC - 4.3 4.75 x TC - 4.0 45.2 68.0 30.1 35.9 24.5 59.8 37.7 45.2 22.5 7.4 Max -- -- -- 39.9 28.5 -- -- -- -- -- Min 36.6 55.5 24.1 29.3 19.9 49.1 30.4 36.6 17.9 5.4 Max -- -- -- 33.3 23.9 -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns 80 MHz Unit 174 tCAH 45.2 -- 36.6 -- ns 175 tAR 83.1 -- 67.9 -- ns 176 tRAL 56.6 -- 46.0 -- ns 177 178 179 tRCS tRCH tRRH 26.5 15.2 0.1 -- 41.3 79.1 124.3 128.3 113.1 68.0 -- -- -- -- -- -- -- -- -- -- 21.2 11.9 -- 0.1 33.3 64.6 101.8 105.1 92.6 55.4 -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns DSP56364 Technical Data, Rev. 4 3-30 Freescale Semiconductor External Memory Expansion Port (Port A) Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 (continued) 66 MHz No. Characteristics3 Symbol Expression4 Min 186 187 188 189 CAS assertion to data not valid (write) RAS assertion to data not valid (write) WR assertion to CAS assertion CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) RD assertion to RAS deassertion RD assertion to data valid tDH tDHR tWCS tCSR 3.25 x TC - 4.0 5.75 x TC - 4.0 5.5 x TC - 4.3 1.5 x TC - 4.0 1.75 x TC - 4.0 8.5 x TC - 4.0 7.5 x TC - 7.5 7.5 x TC - 6.5 193 194 195 1 2 80 MHz Unit Min 36.6 67.9 64.5 14.8 Max -- -- -- -- ns ns ns ns Max -- -- -- -- 45.2 83.1 79.0 18.7 190 tRPC 22.5 -- 17.9 -- ns 191 192 tROH tGA 124.8 -- -- 0.0 11.1 -- -- 106.1 -- -- -- 3.8 102.3 -- -- 0.0 9.1 -- -- -- 87.3 -- -- 3.1 ns ns ns ns ns ns RD deassertion to data not valid3 WR assertion to data active WR deassertion to data high impedance tGZ 0.0 0.75 x TC - 0.3 0.25 x TC The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. 3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t OFF and not tGZ. 4 The asynchronous delays specified in the expressions are valid for DSP56364. 5 Either t RCH or tRRH must be satisfied for read cycles. Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 No. 157 158 159 160 161 162 163 Characteristics3 Random read or write cycle time RAS assertion to data valid (read) CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion RAS assertion pulse width Symbol tRC tRAC tCAC tAA tOFF tRP tRAS 4.25 x TC - 4.0 7.75 x TC - 4.0 Expression4 12 x TC 6.25 x TC - 7.0 3.75 x TC - 7.0 4.5 x TC - 7.0 Min 120.0 -- -- -- 0.0 38.5 73.5 Max -- 55.5 30.5 38.0 -- -- -- Unit ns ns ns ns ns ns ns DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-31 External Memory Expansion Port (Port A) Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 (continued) No. 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 Characteristics3 CAS assertion to RAS deassertion RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion CAS deassertion pulse width Row address valid to RAS assertion RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR5 assertion RAS deassertion to WR5 assertion CAS assertion to WR deassertion RAS assertion to WR deassertion WR assertion pulse width WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) RAS assertion to data not valid (write) WR assertion to CAS assertion CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) Symbol tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC Expression4 5.25 x TC - 4.0 6.25 x TC - 4.0 3.75 x TC - 4.0 2.5 x TC 4.0 1.75 x TC 4.0 5.75 x TC - 4.0 4.25 x TC - 4.0 4.25 x TC - 4.0 1.75 x TC - 4.0 0.75 x TC - 4.0 5.25 x TC - 4.0 7.75 x TC - 4.0 6 x TC - 4.0 3.0 x TC - 4.0 1.75 x TC - 4.0 0.25 x TC - 2.0 5 x TC - 4.2 7.5 x TC - 4.2 11.5 x TC - 4.5 11.75 x TC - 4.3 10.25 x TC - 4.3 5.75 x TC - 4.0 5.25 x TC - 4.0 7.75 x TC - 4.0 6.5 x TC - 4.3 1.5 x TC - 4.0 2.75 x TC - 4.0 Min 48.5 58.5 33.5 21.0 13.5 53.5 38.5 38.5 13.5 3.5 48.5 73.5 56.0 26.0 13.5 0.5 45.8 70.8 110.5 113.2 103.2 53.5 48.5 73.5 60.7 11.0 23.5 Max -- -- -- 29.0 21.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DSP56364 Technical Data, Rev. 4 3-32 Freescale Semiconductor External Memory Expansion Port (Port A) Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 (continued) No. 191 192 193 194 195 1 2 Characteristics3 RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid3 WR assertion to data active WR deassertion to data high impedance Symbol tROH tGA tGZ Expression4 11.5 x TC - 4.0 10 x TC - 7.0 Min 111.0 -- 0.0 Max -- 93.0 -- -- 2.5 Unit ns ns ns ns ns 0.75 x TC - 0.3 0.25 x TC 7.2 -- The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. 3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 4 The asynchronous delays specified in the expressions are valid for DSP56364. 5 Either tRCH or tRRH must be satisfied for read cycles. Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 No. 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 Characteristics3 Random read or write cycle time RAS assertion to data valid (read) CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion RAS assertion pulse width CAS assertion to RAS deassertion RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion CAS deassertion pulse width Row address valid to RAS assertion RAS assertion to row address not valid Symbol tRC tRAC tCAC tAA tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH Expression 16 x TC 8.25 x TC - 5.7 4.75 x TC - 5.7 5.5 x TC - 5.7 0.0 6.25 x TC - 4.0 9.75 x TC - 4.0 6.25 x TC - 4.0 8.25 x TC - 4.0 4.75 x TC - 4.0 3.5 x TC 2 2.75 x TC 2 7.75 x TC - 4.0 6.25 x TC - 4.0 6.25 x TC - 4.0 2.75 x TC - 4.0 Min 160.0 -- -- -- 0.0 58.5 93.5 58.5 78.5 43.5 33.0 25.5 73.5 58.5 58.5 23.5 Max -- 76.8 41.8 49.3 -- -- -- -- -- -- 37.0 29.5 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-33 External Memory Expansion Port (Port A) Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 (continued) No. 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 1 2 Characteristics3 Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR4 assertion RAS deassertion to WR4 assertion CAS assertion to WR deassertion RAS assertion to WR deassertion WR assertion pulse width WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) RAS assertion to data not valid (write) WR assertion to CAS assertion CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid3 WR assertion to data active WR deassertion to data high impedance Symbol tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC tROH tGA tGZ Expression 0.75 x TC - 4.0 6.25 x TC - 4.0 9.75 x TC - 4.0 7 x TC - 4.0 5 x TC - 3.8 1.75 x TC - 3.7 0.25 x TC - 2.0 6 x TC - 4.2 9.5 x TC - 4.2 15.5 x TC - 4.5 15.75 x TC - 4.3 14.25 x TC - 4.3 8.75 x TC - 4.0 6.25 x TC - 4.0 9.75 x TC - 4.0 9.5 x TC - 4.3 1.5 x TC - 4.0 4.75 x TC - 4.0 15.5 x TC - 4.0 14 x TC - 5.7 Min 3.5 58.5 93.5 66.0 46.2 13.8 0.5 55.8 90.8 150.5 153.2 138.2 83.5 58.5 93.5 90.7 11.0 43.5 151.0 -- 0.0 Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 134.3 -- -- 2.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.75 x TC - 0.3 0.25 x TC 7.2 -- The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. 3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. 4 Either t RCH or tRRH must be satisfied for read cycles. DSP56364 Technical Data, Rev. 4 3-34 Freescale Semiconductor External Memory Expansion Port (Port A) 157 162 RAS 167 169 168 170 CAS 171 173 174 175 A0-A17 Row Address 172 177 191 WR 160 159 RD 158 192 Data In AA0476 193 168 179 Column Address 176 166 164 163 165 162 161 D0-D7 Figure 3-15 DRAM Out-of-Page Read Access DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-35 External Memory Expansion Port (Port A) 157 162 163 165 162 RAS 167 169 168 170 CAS 171 173 172 164 166 174 176 A0-A17 Row Address 181 Column Address 175 188 WR 182 180 184 183 RD 187 186 185 194 195 D0-D7 Data Out AA0477 Figure 3-16 DRAM Out-of-Page Write Access DSP56364 Technical Data, Rev. 4 3-36 Freescale Semiconductor Serial Host Interface SPI Protocol Timing 157 162 RAS 190 170 CAS 165 163 162 189 177 WR AA0478 Figure 3-17 DRAM Refresh Access 3.11 Serial Host Interface SPI Protocol Timing Table 3-17 Serial Host Interface SPI Protocol Timing Filter Mode Bypassed Narrow Wide No. 140 Characteristics Tolerable spike width on clock or data in Mode -- Expression -- -- -- 6xTC+46 6xTC+152 6xTC+223 0.5xtSPICC -10 0.5xtSPICC -10 0.5xtSPICC -10 2.5xTC+12 2.5xTC+102 2.5xTC+189 Min -- -- -- 106 212 283 43 96 131 37 127 214 Max 0 50 100 -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns 141 Minimum serial clock cycle = tSPICC(min) Master Bypassed Narrow Wide 142 Serial clock high period Master Bypassed Narrow Wide Slave Bypassed Narrow Wide DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-37 Serial Host Interface SPI Protocol Timing Table 3-17 Serial Host Interface SPI Protocol Timing (continued) No. 143 Characteristics Serial clock low period Mode Master Filter Mode Bypassed Narrow Wide Slave Bypassed Narrow Wide 144 Serial clock rise/fall time Master Slave 146 SS assertion to first SCK edge CPHA = 0 Slave -- -- Bypassed Narrow Wide CPHA = 1 Slave Bypassed Narrow Wide 147 Last SCK edge to SS not asserted Slave Bypassed Narrow Wide 148 Data input valid to SCK edge (data input set-up time) Master/ Slave Bypassed Narrow Wide 149 SCK last sampling edge to data input not valid Master/ Slave Bypassed Narrow Wide 150 151 SS assertion to data out active SS deassertion to data high impedance Slave Slave -- -- Expression 0.5xtSPICC -10 0.5xtSPICC -10 0.5xtSPICC -10 2.5xTC+12 2.5xTC+102 2.5xTC+189 -- -- 3.5xTC+15 0 0 10 0 0 12 102 189 0 MAX{(20-TC), 0} MAX{(40-TC), 0} 2.5xTC+10 2.5xTC+30 2.5xTC+50 2 9 Min 43 96 131 37 127 214 -- -- 50 0 0 10 0 0 12 102 189 0 10 30 35 55 75 2 -- Max -- -- -- -- -- -- 10 2000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DSP56364 Technical Data, Rev. 4 3-38 Freescale Semiconductor Serial Host Interface SPI Protocol Timing Table 3-17 Serial Host Interface SPI Protocol Timing (continued) No. 152 Characteristics SCK edge to data out valid (data out delay time) Mode Master/ Slave Filter Mode Bypassed Narrow Wide 153 SCK edge to data out not valid (data out hold time) Master/ Slave Bypassed Narrow Wide 154 SS assertion to data out valid (CPHA = 0) First SCK sampling edge to HREQ output deassertion Slave -- Expression 2xTC+33 2xTC+123 2xTC+210 TC+5 TC+55 TC+106 TC+33 Min -- -- -- 15 65 116 -- Max 53 143 230 -- -- -- 43 Unit ns ns ns ns ns ns ns 157 Slave Bypassed Narrow Wide 2.5xTC+30 2.5xTC+120 2.5xTC+217 2.5xTC+30 2.5xTC+80 2.5xTC+136 2.5xTC+30 -- -- -- 55 105 161 55 55 145 242 -- -- -- -- ns ns ns ns ns ns ns 158 Last SCK sampling edge to HREQ output not deasserted (CPHA = 1) Slave Bypassed Narrow Wide 159 SS deassertion to HREQ output not deasserted (CPHA = 0) SS deassertion pulse width (CPHA = 0) HREQ in assertion to first SCK edge Slave -- 160 161 Slave Master -- Bypassed TC+6 0.5 x tSPICC + 2.5xTC+43 0.5 xtSPICC + 2.5xTC+43 0.5 xtSPICC + 2.5xTC+43 0 16 121 -- -- ns ns Narrow 174 -- ns Wide 209 -- ns 162 HREQ in deassertion to last SCK sampling edge (HREQ in set-up time) (CPHA = 1) First SCK edge to HREQ in not asserted (HREQ in hold time) Master -- 0 -- ns 163 Master -- 0 0 -- ns Note: Periodically sampled, not 100% tested DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-39 Serial Host Interface SPI Protocol Timing SS (Input) 143 142 SCK (CPOL = 0) (Output) 142 143 SCK (CPOL = 1) (Output) 148 149 MISO (Input) MSB Valid 152 MOSI (Output) 161 163 HREQ (Input) AA0271 MSB 148 LSB Valid 153 LSB 149 141 144 144 144 141 144 Figure 3-18 SPI Master Timing (CPHA = 0) DSP56364 Technical Data, Rev. 4 3-40 Freescale Semiconductor Serial Host Interface SPI Protocol Timing SS (Input) 143 142 SCK (CPOL = 0) (Output) 142 143 SCK (CPOL = 1) (Output) 148 149 MISO (Input) MSB Valid 152 MOSI (Output) 161 163 HREQ (Input) AA0272 MSB 162 LSB Valid 153 LSB 148 149 144 141 144 144 141 144 Figure 3-19 SPI Master Timing (CPHA = 1) DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-41 Serial Host Interface SPI Protocol Timing SS (Input) 143 142 SCK (CPOL = 0) (Input) 146 142 143 SCK (CPOL = 1) (Input) 154 150 MISO (Output) 148 149 MOSI (Input) MSB Valid 157 HREQ (Output) AA0273 LSB Valid 159 153 MSB 148 149 152 153 151 LSB 141 144 144 144 141 144 160 147 Figure 3-20 SPI Slave Timing (CPHA = 0) DSP56364 Technical Data, Rev. 4 3-42 Freescale Semiconductor Serial Host Interface SPI Protocol Timing SS (Input) 143 142 SCK (CPOL = 0) (Input) 146 142 143 SCK (CPOL = 1) (Input) 152 150 MISO (Output) 148 149 MOSI (Input) MSB Valid 157 HREQ (Output) AA0274 LSB Valid 158 MSB 148 149 152 153 151 LSB 144 144 144 141 144 147 Figure 3-21 SPI Slave Timing (CPHA = 1) DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-43 Serial Host Interface (SHI) I2C Protocol Timing 3.12 Serial Host Interface (SHI) I2C Protocol Timing Table 3-18 SHI I2C Protocol Timing Standard I2C1 Standard-Mode Min Max Fast-Mode Unit Max No. Characteristics Symbol/ Expression Min Tolerable spike width on SCL or SDA * Filters bypassed * Narrow filters enabled * Wide filters enabled 171 SCL clock frequency 172 Bus free time 173 Start condition set-up time 174 Start condition hold time 175 SCL low period 176 SCL high period 177 SCL and SDA rise time 178 SCL and SDA fall time 179 Data set-up time 180 Data hold time 181 Stop condition set-up time 182 Capacitive load for each line 183 DSP clock frequency * Filters bypassed * Narrow filters enabled * Wide filters enabled 184 HREQ in deassertion to last SCL edge (HREQ in set-up time) -- -- -- -- FSCL TBUF TSU;STA THD;STA TLOW THIGH TR TF TSU;DAT THD;DAT TSU;STO Cb FDSP 10.6 11.8 13.1 tSU;RQI 0.0 -- -- -- -- 28.5 39.7 61.0 0.0 -- -- -- -- MHz MHz MHz ns -- 4.7 4.7 4.0 4.7 4.0 -- -- 250 0.0 4.0 -- 0 50 100 100 -- -- -- -- -- 1000 300 -- -- -- 400 -- -- -- -- 1.3 0.6 0.6 1.3 1.3 20 + 0.1 x Cb 20 + 0.1 x Cb 100 0.0 0.6 -- 0 50 100 400 -- -- -- -- -- 300 300 -- 0.9 -- 400 ns ns ns kHz s s s s s ns ns ns s s pF DSP56364 Technical Data, Rev. 4 3-44 Freescale Semiconductor Serial Host Interface (SHI) I2C Protocol Timing Table 3-18 SHI I2C Protocol Timing (continued) Standard I2C1 Standard-Mode Min 186 First SCL sampling edge to HREQ output deassertion * Filters bypassed * Narrow filters enabled * Wide filters enabled 187 Last SCL edge to HREQ output not deasserted * Filters bypassed * Narrow filters enabled * Wide filters enabled 188 HREQ in assertion to first SCL edge TNG;RQO 2 x TC + 30 2 x TC + 120 2 x TC + 208 TAS;RQO 2 x TC + 30 2 x TC + 80 2 x TC + 135 TAS;RQI 0.5 x TI2CCP 0.5 x TC - 21 Max Fast-Mode Unit Max ns No. Characteristics Symbol/ Expression Min -- -- -- 50 140 228 -- -- -- 50 140 228 ns ns ns ns 50 100 155 -- -- -- 50 100 155 -- -- -- ns ns ns ns * Filters bypassed * Narrow filters enabled * Wide filters enabled 1 4327 4282 4238 -- -- -- 927 882 838 -- -- -- ns ns ns RP (min) = 1.5 k3/4 3.12.1 Programming the Serial Clock 2 The programmed serial clock cycle, T I CCP, is specified by the value of the HDM[5:0] and HRS bits of the HCKR (SHI clock control register). The expression for T I CCP is 2 T where I CCP 2 = [ T C x 2 x ( HDM [ 7 :0 ] + 1 ) x ( 7 x ( 1 - HRS ) + 1 ) ] HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed. HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 64 (HDM[5:0] = 0 to $3F) may be selected. DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-45 Serial Host Interface (SHI) I2C Protocol Timing In I2C mode, the user may select a value for the programmed serial clock cycle from 6 x T C ( if HDMS [ 5 :0 ] = $02 and HRS = 1 ) to 4096 x T C ( if HDMS [ 7 :0 ] = $FF and HRS = 0 ) The programmed serial clock cycle (TI CCP ), SCL rise time (TR), and the filters selected should be chosen in order to achieve the desired SCL frequency, as shown in Table 3-19. 2 Table 3-19 SCL Serial Clock Cycle generated as Master Filters bypassed Narrow filters enabled Wide filters enabled TI2CCP + 2.5 x TC + 45ns + TR TI2CCP + 2.5 x TC + 135ns + TR TI2CCP + 2.5 x TC + 223ns + TR EXAMPLE: For DSP clock frequency of 100 MHz (i.e. TC = 10ns), operating in a standard-mode I2C environment (FSCL = 100 KHz (i.e. TSCL = 10s), TR = 1000ns), with filters bypassed T Choosing HRS = 0 gives HDM [ 7 :0 ] = ( 8930ns ) ( 2 x 10ns x 8 ) - 1 = 55.8 Thus the HDM[7:0] value should be programmed to $38 (=56). 171 173 SCL 177 172 179 SDA Stop Start 174 189 188 HREQ AA0275 MSB 186 184 187 LSB 182 ACK 183 Stop 178 180 176 175 I CCP 2 = 10s - 2.5 x 10ns - 45ns - 1000ns = 893ns Figure 3-22 I2C Timing DSP56364 Technical Data, Rev. 4 3-46 Freescale Semiconductor Enhanced Serial Audio Interface Timing 3.13 No. 430 Enhanced Serial Audio Interface Timing Table 3-20 Enhanced Serial Audio Interface Timing Characteristics1, 2, 3 Clock cycle5 Symbol tSSICC Expression 4 x TC 3 x TC TXC:max[3*tc; t454] Min 40.0 30.0 40.0 Max -- -- -- Condtion4 i ck x ck x ck ns -- 2 x TC - 10.0 1.5 x TC 10.0 15.0 -- -- ns -- 2 x TC - 10.0 1.5 x TC -- -- 10.0 15.0 -- -- -- -- 37.0 22.0 37.0 22.0 39.0 24.0 39.0 24.0 36.0 21.0 37.0 22.0 -- -- -- -- -- -- -- -- x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck x ck i ck x ck i ck a x ck i ck a ns ns ns ns ns ns ns ns ns ns Unit ns 431 Clock high period * For internal clock * For external clock 432 Clock low period * For internal clock * For external clock 433 RXC rising edge to FSR out (bl) high 434 RXC rising edge to FSR out (bl) low -- -- -- -- 435 RXC rising edge to FSR out (wr) high6 -- -- -- -- 436 RXC rising edge to FSR out (wr) low6 -- -- -- -- 437 RXC rising edge to FSR out (wl) high -- -- -- -- 438 RXC rising edge to FSR out (wl) low -- -- -- -- 439 Data in setup time before RXC (SCK in synchronous mode) falling edge Data in hold time after RXC falling edge -- -- 0.0 19.0 440 -- -- 5.0 3.0 441 FSR input (bl, wr) high before RXC falling edge6 FSR input (wl) high before RXC falling edge -- -- 23.0 1.0 442 -- -- 1.0 23.0 DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-47 Enhanced Serial Audio Interface Timing Table 3-20 Enhanced Serial Audio Interface Timing (continued) No. 443 Characteristics1, 2, 3 FSR input hold time after RXC falling edge Symbol -- Expression -- Min 3.0 0.0 444 Flags input setup before RXC falling edge -- -- 0.0 19.0 445 Flags input hold time after RXC falling edge -- -- 6.0 0.0 446 TXC rising edge to FST out (bl) high -- -- -- -- 447 TXC rising edge to FST out (bl) low -- -- -- -- 448 TXC rising edge to FST out (wr) high6 -- -- -- -- 449 TXC rising edge to FST out (wr) low6 -- -- -- -- 450 TXC rising edge to FST out (wl) high -- -- -- -- 451 TXC rising edge to FST out (wl) low -- -- -- -- 452 TXC rising edge to data out enable from high impedance TXC rising edge to transmitter #0 drive enable assertion TXC rising edge to data out valid -- -- -- -- -- -- -- -- -- 23 + 0.5 x TC 21.0 455 TXC rising edge to data out high impedance7 -- -- -- -- -- -- 456 TXC rising edge to transmitter #0 drive enable deassertion7 FST input (bl, wr) setup time before TXC falling edge6 FST input (wl) to data out enable from high impedance -- -- -- -- -- -- 2.0 21.0 -- -- -- Max -- -- -- -- -- -- 29.0 15.0 31.0 17.0 31.0 17.0 33.0 19.0 30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 28.0 21.0 31.0 16.0 34.0 20.0 -- -- 27.0 Condtion4 x ck i ck a x ck i ck s x ck i ck s x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit ns 453 454 457 458 DSP56364 Technical Data, Rev. 4 3-48 Freescale Semiconductor Enhanced Serial Audio Interface Timing Table 3-20 Enhanced Serial Audio Interface Timing (continued) No. 459 Characteristics1, 2, 3 FST input (wl) to transmitter #0 drive enable assertion FST input (wl) setup time before TXC falling edge FST input hold time after TXC falling edge Symbol -- Expression -- Min -- Max 31.0 Condtion4 -- Unit ns 460 -- -- 2.0 21.0 -- -- -- -- 32.0 18.0 -- 27.5 27.5 x ck i ck x ck i ck x ck i ck ns 461 -- -- 4.0 0.0 ns 462 Flag output valid after TXC rising edge -- -- -- -- ns 463 464 465 1 2 HCKR/HCKT clock cycle HCKT input rising edge to TXC output HCKR input rising edge to RXC output -- -- -- -- -- -- 40.0 -- -- ns ns ns 3 4 5 6 7 VCC = 3.16 V 0.16 V; TJ = 0C to +105C, CL = 50 pF. i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that TXC and RXC are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that TXC and RXC are the same clock) bl = bit length wl = word length wr = word length relative TXC(SCKT pin) = transmit clock RXC(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) = receive frame sync HCKT(HCKT pin) = transmit high speed clock HCKR(HCKR pin) = receive high speed clock For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. Periodically sampled and not 100% tested DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-49 Enhanced Serial Audio Interface Timing 430 TXC (Input/Output) 431 432 446 FST (Bit) Out 447 450 FST (Word) Out 454 452 Data Out First Bit 459 Last Bit 454 451 455 Transmitter #0 Drive Enable 457 FST (Bit) In 453 461 456 458 460 461 FST (Word) In 462 Flags Out See Note Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. AA0490 Figure 3-23 ESAI Transmitter Timing DSP56364 Technical Data, Rev. 4 3-50 Freescale Semiconductor Enhanced Serial Audio Interface Timing 430 431 RXC (Input/Output) 433 FSR (Bit) Out 437 FSR (Word) Out 440 439 Data In 441 FSR (Bit) In 442 FSR (Word) In 444 Flags In AA0491 445 443 443 First Bit Last Bit 438 432 434 Figure 3-24 ESAI Receiver Timing HCKT SCKT(output) 463 464 Figure 3-25 ESAI HCKT Timing DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-51 GPIO Timing HCKR SCKR (output) 463 465 Figure 3-26 ESAI HCKR Timing 3.14 No. 4902 491 492 493 4942 495 496 1 2 GPIO Timing Table 3-21 GPIO Timing Characteristics1 EXTAL edge to GPIO out valid (GPIO out delay time) EXTAL edge to GPIO out not valid (GPIO out hold time) GPIO In valid to EXTAL edge (GPIO in set-up time) EXTAL edge to GPIO in not valid (GPIO in hold time) Fetch to EXTAL edge before GPIO change GPIO out rise time GPIO out fall time 6.75 x TC-1.8 -- -- Expression Min -- 4.8 10.2 1.8 65.7 -- -- Max 32.8 -- -- -- -- 13 13 Unit ns ns ns ns ns ns ns VCC = 3.3 V 0.16 V; TJ = 0C to +105C, CL = 50 pF Valid only when PLL enabled with multiplication factor equal to one. DSP56364 Technical Data, Rev. 4 3-52 Freescale Semiconductor JTAG Timing EXTAL (Input) 490 491 GPIO (Output) 492 GPIO (Input) Valid 493 A0-A17 494 Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of GPIO data register. GPIO (Output) 495 496 Figure 3-27 GPIO Timing 3.15 JTAG Timing Table 3-22 JTAG Timing1. 2 All frequencies No. Characteristics Min Max 22.0 -- -- 3.0 -- -- 40.0 40.0 -- TCK frequency of operation (1/(TC x 3); maximum 22 MHz) TCK cycle time in Crystal mode TCK clock pulse width measured at 1.5 V TCK rise and fall times Boundary scan input data setup time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data setup time Unit 500 501 502 503 504 505 506 507 508 0.0 45.0 20.0 0.0 5.0 24.0 0.0 0.0 5.0 MHz ns ns ns ns ns ns ns ns DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-53 JTAG Timing Table 3-22 JTAG Timing1. 2 (continued) All frequencies No. Characteristics Min 509 510 511 1 2 Unit Max -- 44.0 44.0 ns ns ns TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance 25.0 0.0 0.0 VCC = 3.3 V 0.16 V; TJ = 0C to +105C, CL = 50 pF All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. 501 502 TCK (Input) VIH VIL 503 503 AA0496 VM 502 VM Figure 3-28 Test Clock Input Timing Diagram TCK (Input) VIH VIL 504 505 Data Inputs 506 Data Outputs 507 Data Outputs 506 Data Outputs Input Data Valid Output Data Valid Output Data Valid AA0497 Figure 3-29 Boundary Scan (JTAG) Timing Diagram DSP56364 Technical Data, Rev. 4 3-54 Freescale Semiconductor JTAG Timing TCK (Input) TDI TMS (Input) VIH VIL 508 Input Data Valid 510 509 TDO (Output) 511 TDO (Output) 510 TDO (Output) Output Data Valid Output Data Valid AA0498 Figure 3-30 Test Access Port Timing Diagram DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 3-55 JTAG Timing NOTES DSP56364 Technical Data, Rev. 4 3-56 Freescale Semiconductor 4 4.1 Packaging Pin-out and Package Information This section provides information about the available package for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 2, "Signal/Connection Descriptions" are allocated for the package. The DSP56364 is available in a 100-pin TQFP package. Table 4-1 and Table 4-2show the pin/name assignments for the packages. 4.1.1 TQFP Package Description Top view of the 100-pin TQFP package is shown in Figure 4-1 with its pin-outs. The 100-pin TQFP package mechanical drawing is shown in Figure 4-2. DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 4-1 Pin-out and Package Information NC NC NC GPIO3 GPIO2 GPIO1 GPIO0 GNDD VCCD TDI D7 D6 D5 D4 D3 78 D2 77 TMS TCK GNDS VCCS VCCHQ 100 99 98 97 96 95 94 93 92 91 90 89 88 87 VCCLQ TDO GNDQ 86 85 84 83 82 81 80 79 MODD MODB MODA FST FSR SCKT SCKR VCCS GNDS HCKT VCCLQ GNDQ HCKR SDO0 VCCHQ SDO1 SDO2/SDI3 SDO3/SDI2 SDO4/SDI1 SDO5/SDI0 VCCS GNDS SS/HA2 MOSI/HA0 MISO/SDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DSP56364 100-Pin TQPF 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 D1 D0 A17 A16 GNDA VCCA A15 A14 A13 A12 VCCLQ GNDQ GNDA VCCA A11 VCCQH A10 A9 A8 A7 GNDA VCCA A6 A5 A4 A3 RESET EXTAL NC SCK/SCL PINIT/NMI VCCQL WR RD VCCC AA1 AA0 A0 A1 GNDC PCAP TA VCCP CAS GNDP VCCA VCCHQ Figure 4-1 DSP56364 100-Pin Thin Quad Flat Pack (TQFP), Top View DSP56364 Technical Data, Rev. 4 4-2 Freescale Semiconductor GNDQ GNDA HREQ A2 Pin-out and Package Information Table 4-1 DSP56364 100-Pin TQFP Signal Identification by Pin Number Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Signal Name MODD/IRQD MODB/IRQB MODA/IRQA FST FSR SCKT SCKR VCCS GNDS HCKT VCCLQ GNDQ HCKR SDO0 VCCHQ SDO1 SDO2/SDI3 SDO3/SDI2 SDO4/SDI1 SDO5/SDI0 VCCS GNDS SS/HA2 MOSI/HA0 MISO/SDA Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal Name SCK/SCL HREQ PINIT/NMI RESET No Connect VCCP PCAP GNDP EXTAL VCCHQ GNDQ VCCLQ TA CAS WR Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 A3 A4 A5 A6 VCCA GNDA A7 A8 A9 A10 VCCHQ A11 VCCA GNDA GNDQ VCCLQ A12 A13 A14 A15 VCCA GNDA A16 A17 D0 Signal Name Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Signal Name D1 D2 D3 VCCD GNDD D4 D5 D6 D7 No Connect No Connect VCCLQ GNDQ VCCHQ No Connect GPIO0 VCCS GNDS GPIO1 GPIO2 GPIO3 TDO TDI TCK TMS RD VCCC GNDC AA1/RAS1 AA0/RAS0 A0 A1 VCCQ GNDQ A2 Note: Signal names are based on configured functionality. Most pins supply a single signal. Some pins provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is deasserted, but act as interrupt lines during operation. DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 4-3 Pin-out and Package Information Table 4-2 DSP56364 100-Pin TQFP Signal Identification by Name Signal Name A0 A1 A10 A11 A12 A13 A14 A15 A16 A17 A2 A3 A4 A5 A6 A7 A8 A9 AA0 AA1 CAS D0 D1 D2 D3 Pin No. 46 47 60 62 67 68 69 70 73 74 50 51 52 53 54 57 58 59 45 44 39 75 76 77 78 Signal Name D4 D5 D6 D7 EXTAL FSR FST GNDA GNDA GNDA GNDA GNDC GNDD GNDP GNDQ GNDQ GNDQ GNDQ GNDS GNDS GNDS GPIO0 GPIO1 GPIO2 GPIO3 Pin No. 81 82 83 84 34 5 4 49 56 64 72 43 80 33 12 36 65 88 9 22 93 91 94 95 96 Signal Name HCKR HCKT HREQ MISO/SDA MODA/IRQA MODB/IRQB MODD/IRQD MOSI/HA0 No Connect No Connect No Connect No Connect PCAP PINIT/NMI RD RESET SCK/SCL SCKR SCKT SDO0 SDO1 SDO5/SDI0 SS/HA2 SDO2/SDI3 SDO3/SDI2 Pin No. 13 10 27 25 3 2 1 24 30 85 86 90 32 28 41 29 26 7 6 14 16 20 23 17 18 Signal Name SDO4/SDI1 TA TCK TDI TD0 TMS VCCA VCCA VCCA VCCA VCCC VCCD VCCHQ VCCHQ VCCHQ VCCHQ VCCLQ VCCLQ VCCLQ VCCLQ VCCP VCCS VCCS VCCS WR Pin No. 19 38 99 98 97 100 48 55 63 71 42 79 15 35 61 89 11 37 66 87 31 8 21 92 40 DSP56364 Technical Data, Rev. 4 4-4 Freescale Semiconductor Pin-out and Package Information 4.1.2 TQFP Package Mechanical Drawing Figure 4-2 DSP56364 100-pin TQFP Package DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 4-5 Pin-out and Package Information DSP56364 Technical Data, Rev. 4 4-6 Freescale Semiconductor 5 5.1 Design Considerations Thermal Design Considerations T J = T A + ( P D x R JA ) An estimation of the chip junction temperature, TJ, in C can be obtained from the following equation: Where: TA = ambient temperature C RqJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package W Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance. R JA = R JC + R CA Where: RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages. * To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 5-1 Electrical Design Considerations * * To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. If the temperature of the package case (TT) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation: ( TJ - TT ) PD As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, thermal characterization parameter or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 5.2 Electrical Design Considerations CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). The suggested value for a pullup or pulldown resistor is 10 k ohm. Use the following list of recommendations to assure correct DSP operation: * Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the board ground to each GND pin. * Use at least six 0.01-0.1 F bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. * Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 1.2 cm (0.5 inch) per capacitor lead. * Use at least a four-layer PCB with two inner layers for VCC and GND. * Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, IRQD, and TA pins. Maximum PCB trace lengths on the order of 15 cm (6 inches) are recommended. * Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. DSP56364 Technical Data, Rev. 4 5-2 Freescale Semiconductor Power Consumption Considerations * * * * * All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except for the three pins with internal pull-up resistors (TMS, TDI, TCK). Take special care to minimize noise levels on the VCCP and GNDP pins. If multiple DSP56364 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. RESET must be asserted when the chip is powered up. A stable EXTAL signal must be supplied before deassertion of RESET. At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip VCC never exceeds 3.95 V. 5.3 Power Consumption Considerations Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by the following formula: I = CxVxf where C V f = node/pin capacitance = voltage swing = frequency of node/pin toggle Example 1. Current Consumption For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 100 MHz clock, toggling at its maximum possible rate (50 MHz), the current consumption is I = 50 x 10 - 12 x 3.3 x 50 x 10 = 8.25mA 6 The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses on best-case operation conditions, which is not necessarily a real application case. The typical internal current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions. For applications that require very low current consumption, do the following: * Set the EBD bit when not accessing external memory. * Minimize external memory accesses and use internal memory accesses. * Minimize the number of pins that are switching. * Minimize the capacitive load on the pins. * Connect the unused inputs to pull-up or pull-down resistors. * Disable unused peripherals. One way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP). DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 5-3 PLL Performance Issues A benchmark power consumption test algorithm is listed in Appendix A, "IBIS Model". Use the test algorithm, specific test current measurements, and the following equation to derive the current per MIPS value. I MIPS = I MHz = ( I typF2 - I typF1 ) ( F2 - F1 ) where: ItypF2 ItypF1 F2 F1 = = = = current at F2 current at F1 high frequency (any specified operating frequency) low frequency (any specified operating frequency lower than F2) NOTE F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application. 5.4 PLL Performance Issues The following explanations should be considered as general observations on expected PLL behavior. There is no testing that verifies these exact numbers. These observations were measured on a limited number of parts and were not verified over the entire temperature and voltage ranges. 5.4.1 Input (EXTAL) Jitter Requirements The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL is slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be 2%. The phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values. DSP56364 Technical Data, Rev. 4 5-4 Freescale Semiconductor 6 Ordering Information Table 6-1 Ordering Information1, 2 Part DSP56364 Supply Voltage 3.3 V Package Type Thin quad flat pack (TQFP) Quad flat pack (QFP) 1 Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and to place an order. Pin Count 100 112 Frequency (MHz) 100 100 Order Number XCB56364FU100 XCB56364PV100 The DSP56364 can include factory-programmed ROM. The listed `B' ROM code is a generic unused ROM available to any customer. Variations will be supported for Dolby digital (AC-3), DTS, MPEG2, and other features. These products are only available to authorized licensees of those technologies. Please consult the web site at www.dspaudio.freescale.com for current availability. 2 Future products in the DSP56364 family may include other ROM-based options. For additional information on future part development, or to request customer-specific ROM-based support, call your local Freescale Semiconductor sales office or authorized distributor. DSP56364 Technical Data, Rev. 4 Freescale Semiconductor 6-1 NOTES DSP56364 Technical Data, Rev. 4 6-2 Freescale Semiconductor Appendix A IBIS Model IBIS Model [IBIS Ver] 3.2 [File name] 56364_e.ibs [File Rev] e [Date] Feb 13, 2002 [Component] 56364 [Manufacturer] Freescale SEMI CONDUCTOR Ltd. [Package] | variable typ min max R_pkg 45.0m 22.0m 75.0m L_pkg 2.5nH 1.1nH 4.3nH C_pkg 1.3pF 1.2pF 1.4pF [Pin] signal_name model_name R_pin 1 irqd_ ipad5v_io 2 irqb_ ipad5v_io 3 irqa_ ipad5v_io 4 fst ipad5v_io 5 fsr ipad5v_io 6 sckt ipad5v_io 7 sckr ipad5v_io 8 vccs power 9 gnds gnd 10 hckt ipad5v_io 11 vcclq power 12 gndq gnd 13 hckr ipad5v_io 14 sdo0 ipad5v_io 15 vcchq power 16 sdo1 ipad5v_io 17 sdo2/sdi3 ipad5v_io 18 sdo3/sdi2 ipad5v_io 19 sdo4/sdi1 ipad5v_io 20 sdo5/sdi0 ipad5v_io 21 vccs power 22 gnds gnd 23 ss_/ha2 ipad5v_io 24 mosi/ha0 ipad5v_io 25 miso/sda ipad5i_io 26 sck/scl ipad5i_io 27 hreq_ ipad5i_io 28 pinit/nmi_ ipad5v_io 29 reset_ ipad5v_io 31 vccp power 32 pcap power 33 gndp gnd 34 extal ipadex_i 35 vcchq power L_pin C_pin DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-1 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 87 88 89 91 92 93 gndq vcclq ta_ cas_ wr_ rd_ vccc gndc aa1/ras1_ aa0/ras0_ a0 a1 vccq gndq a2 a3 a4 a5 a6 vcca gnda a7 a8 a9 a10 vcchq a11 vcca gnda gndq vcclq a12 a13 a14 a15 vcca gnda a16 a17 d0 d1 d2 d3 vccd gndd d4 d5 d6 d7 vcclq gndq vcchq gpio0 vccs gnds gnd power ipadn_io ipadm_3st ipadn_io ipadn_io power gnd ipado_3st ipado_3st ipada_3st ipada_3st power gnd ipada_3st ipada_3st ipada_3st ipada_3st ipada_3st power gnd ipada_3st ipada_3st ipada_3st ipada_3st power ipada_3st power gnd gnd power power ipada_3st ipada_3st ipada_3st power gnd ipada_3st ipada_3st ipadd_io ipadd_io ipadd_io ipadd_io power gnd ipadd_io ipadd_io ipadd_io ipadd_io power gnd power ipad5v_io power gnd DSP56364 Technical Data, Rev. 4 A-2 Freescale Semiconductor 94 95 96 97 98 99 100 gpio1 gpio2 gpio3 tdo tdi tck tms ipad5v_io ipad5v_io ipad5v_io ipad5f_io ipad5f_io ipad5f_io ipad5f_io [Model] ipad5f_io | "" Model_type I/O Vinl = 0.8 Vinh = 2 | variable typ min max C_comp 1.96p 1.87p 2.06p | variable typ min max [Temperature Range] 40.0 0.0 120.0 | variable typ min max [Voltage Range] 3.30V 3.00V 3.60V | [Pulldown] | pulldown in the table = pulldown subtract gnd_clamp |Voltage I(typ) I(min) I(max) | -3.30V -142.303u -76.239u -215.182u -3.20V -149.700u -80.226u -226.432u -3.10V -157.861u -84.616u -238.866u -3.00V -166.908u -89.472u -252.678u -2.90V -176.992u -94.869u -268.107u -2.80V -188.295u -100.900u -285.446u -2.70V -201.049u -107.679u -305.068u -2.60V -215.545u -115.349u -327.446u -2.50V -232.155u -124.094u -353.191u -2.40V -251.367u -134.145u -383.107u -2.30V -273.825u -145.808u -418.273u -2.20V -300.403u -159.488u -460.167u -2.10V -332.314u -175.737u -510.874u -2.00V -371.286u -195.318u -573.418u -1.90V -419.868u -219.325u -652.360u -1.80V -481.968u -249.369u -754.892u -1.70V -563.882u -287.925u -893.013u -1.60V -676.382u -338.973u -1.088m -1.50V -839.410u -409.300u -1.383m -1.40V -1.094m -511.367u -1.873m -1.30V -1.537m -670.350u -2.819m -1.20V -2.451m -943.845u -5.162m -1.10V -4.857m -1.486m -12.214m -1.00V -10.606m -2.746m -20.764m -0.90V -14.267m -5.259m -21.749m -0.80V -13.851m -7.108m -20.142m -0.70V -12.481m -7.168m -18.211m -0.60V -10.883m -6.348m -15.981m -0.50V -9.156m -5.339m -13.503m -0.40V -7.378m -4.288m -10.922m -0.30V -5.572m -3.224m -8.282m -0.20V -3.741m -2.154m -5.584m DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-3 -0.10V 0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.00V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.00V 3.10V 3.20V 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.00V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.00V 5.10V 5.20V 5.30V -1.885m 1.898p 1.857m 3.630m 5.323m 6.936m 8.467m 9.915m 11.275m 12.546m 13.723m 36.925m 39.391m 41.612m 43.585m 45.305m 46.773m 47.997m 48.985m 49.733m 50.257m 50.612m 50.858m 51.040m 51.182m 51.302m 51.405m 51.497m 51.581m 51.658m 51.727m 51.757m 51.229m 49.190m 49.441m 51.034m 54.363m 57.165m 58.834m 60.328m 61.725m 63.035m 64.319m 65.598m 66.836m 67.999m 69.069m 70.046m 70.938m 71.751m 72.476m 73.089m 73.531m 73.651m 72.901m -1.080m 1.419p 1.057m 2.064m 3.023m 3.935m 4.798m 5.611m 6.371m 7.078m 7.726m 20.745m 22.074m 23.244m 24.247m 25.079m 25.741m 26.251m 26.633m 26.905m 27.092m 27.223m 27.321m 27.399m 27.465m 27.522m 27.572m 27.618m 27.657m 27.674m 27.587m 27.577m 28.700m 30.042m 31.171m 32.199m 33.153m 34.039m 34.872m 35.686m 36.495m 37.291m 38.051m 38.755m 39.394m 39.962m 40.453m 40.840m 41.065m 40.952m 40.067m 39.395m 39.313m 39.358m 39.410m -2.825m 1.871p 2.800m 5.482m 8.052m 10.508m 12.849m 15.073m 17.176m 19.155m 21.011m 56.704m 60.708m 64.383m 67.726m 70.735m 73.414m 75.766m 77.783m 79.441m 80.724m 81.651m 82.294m 82.744m 83.074m 83.332m 83.543m 83.724m 83.884m 84.030m 84.165m 84.290m 84.409m 84.515m 84.491m 81.077m 79.736m 80.276m 82.430m 85.482m 91.743m 94.219m 96.276m 98.249m 100.059m 101.849m 103.628m 105.345m 106.956m 108.448m 109.826m 111.106m 112.297m 113.400m 114.401m DSP56364 Technical Data, Rev. 4 A-4 Freescale Semiconductor 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.00V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V 71.005m 70.389m 70.321m 70.361m 70.422m 70.489m 70.557m 70.624m 70.690m 70.753m 70.817m 70.881m 70.949m 39.460m 39.508m 39.552m 39.595m 39.634m 39.672m 39.708m 39.743m 39.777m 39.812m 39.848m 39.886m 39.929m 115.267m 115.917m 116.139m 114.582m 111.344m 110.612m 110.449m 110.455m 110.515m 110.595m 110.686m 110.783m 110.885m | [Pullup] | pullup in the table = pullup subtract power_clamp |Voltage I(typ) I(min) I(max) | -3.30V 75.797u 7.914u 161.477u -3.20V 90.464u 17.699u 181.779u -3.10V 105.160u 27.445u 202.314u -3.00V 119.836u 37.119u 223.007u -2.90V 134.451u 46.694u 243.785u -2.80V 148.966u 56.144u 264.581u -2.70V 163.342u 65.447u 285.332u -2.60V 177.543u 74.582u 305.982u -2.50V 191.536u 83.527u 326.474u -2.40V 205.285u 92.262u 346.757u -2.30V 218.754u 100.766u 366.776u -2.20V 231.907u 109.016u 386.478u -2.10V 244.706u 116.988u 405.807u -2.00V 257.106u 124.659u 424.699u -1.90V 269.061u 131.998u 443.089u -1.80V 280.519u 138.978u 460.899u -1.70V 291.423u 145.565u 478.046u -1.60V 301.710u 151.723u 494.457u -1.50V 311.348u 157.417u 521.406u -1.40V 729.899u 162.626u 1.612m -1.30V 10.510m 445.517u 14.832m -1.20V 9.629m 6.444m 13.576m -1.10V 8.670m 5.833m 12.231m -1.00V 7.693m 5.190m 10.854m -0.90V 6.732m 4.551m 9.483m -0.80V 5.825m 3.942m 8.169m -0.70V 5.004m 3.382m 6.971m -0.60V 4.261m 2.869m 5.921m -0.50V 3.549m 2.381m 4.953m -0.40V 2.841m 1.902m 3.978m -0.30V 2.135m 1.426m 2.987m -0.20V 1.437m 951.489u 2.003m -0.10V 722.340u 478.341u 1.005m -0.00V 22.329p 3.311p 24.081p 0.10V -708.556u -465.927u -990.647u 0.20V -1.377m -903.637u -1.943m 0.30V -2.007m -1.319m -2.832m DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-5 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.00V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.00V 3.10V 3.20V 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.00V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.00V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V -2.614m -3.192m -3.738m -4.253m -4.736m -5.185m -5.600m -5.980m -6.324m -6.631m -29.730m -30.749m -31.630m -32.393m -33.055m -33.632m -34.135m -34.575m -34.960m -35.302m -35.608m -35.884m -36.137m -36.370m -36.586m -36.788m -36.978m -37.157m -37.327m -37.489m -37.643m -37.791m -37.933m -38.070m -38.202m -38.332m -38.460m -38.590m -38.714m -38.828m -38.949m -39.076m -39.211m -39.357m -39.516m -39.693m -39.893m -40.121m -40.384m -40.689m -41.043m -41.444m -41.886m -42.370m -42.899m -1.710m -2.079m -2.423m -2.742m -3.037m -3.305m -3.547m -3.762m -3.948m -17.709m -18.279m -18.747m -19.131m -19.454m -19.730m -19.973m -20.188m -20.381m -20.556m -20.715m -20.861m -20.997m -21.123m -21.241m -21.352m -21.457m -21.556m -21.650m -21.741m -21.827m -21.909m -21.989m -22.067m -22.143m -22.216m -22.284m -22.352m -22.420m -22.490m -22.561m -22.635m -22.713m -22.798m -22.892m -22.997m -23.116m -23.253m -23.411m -23.595m -23.801m -24.032m -24.288m -24.570m -24.880m -25.217m -3.702m -4.537m -5.336m -6.096m -6.817m -7.499m -8.139m -8.737m -9.292m -9.802m -10.265m -45.983m -47.620m -49.086m -50.392m -51.551m -52.571m -53.463m -54.240m -54.917m -55.510m -56.035m -56.505m -56.932m -57.322m -57.683m -58.019m -58.334m -58.631m -58.913m -59.181m -59.436m -59.681m -59.916m -60.142m -60.361m -60.573m -60.780m -60.986m -61.194m -61.406m -61.623m -61.819m -62.024m -62.254m -62.506m -62.785m -63.098m -63.453m -63.860m -64.330m -64.874m -65.505m -66.214m -66.983m DSP56364 Technical Data, Rev. 4 A-6 Freescale Semiconductor 5.90V 6.00V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V | [GND_clamp] | |Voltage | -3.30V -3.20V -3.10V -2.90V -2.80V -2.70V -2.60V -2.50V -2.40V -2.30V -2.20V -2.10V -1.90V -1.80V -1.70V -1.60V -1.50V -1.40V -1.30V -1.20V -1.10V -0.90V -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V 0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.10V 1.20V -43.473m -44.095m -44.769m -45.498m -46.287m -47.140m -48.049m -48.990m -25.585m -25.983m -26.415m -26.884m -27.390m -27.929m -28.487m -29.080m -67.815m -68.711m -69.678m -70.721m -71.848m -73.065m -74.374m -75.748m I(typ) -1.875 -1.793 -1.711 -1.548 -1.466 -1.385 -1.303 -1.221 -1.140 -1.059 -977.735m -896.773m -735.446m -655.171m -575.242m -495.760m -416.878m -338.839m -262.067m -187.395m -116.756m -16.024m -2.254m -476.015u -85.877u -8.033u -432.304n -20.874n -964.564p -72.583p -33.685p -27.665p -22.754p -18.303p -14.129p -9.979p -5.833p -1.689p 2.454p 6.596p 14.877p 19.017p I(min) -1.074 -1.029 -983.765m -893.931m -849.071m -804.256m -759.489m -714.777m -670.127m -625.548m -581.048m -536.642m -448.177m -404.164m -360.342m -316.758m -273.482m -230.618m -188.327m -146.891m -106.839m -37.029m -14.319m -2.883m -295.354u -33.637u -3.576u -340.944n -30.895n -2.560n -210.508p -30.628p 13.546p 48.356p 81.869p 114.849p 147.499p 179.924p 212.188p 244.335p 308.388p 340.335p I(max) -2.155 -2.059 -1.963 -1.771 -1.675 -1.579 -1.483 -1.388 -1.292 -1.197 -1.102 -1.007 -817.634m -723.409m -629.587m -536.295m -443.730m -352.222m -262.384m -175.533m -95.231m -6.612m -2.370m -845.181u -147.930u -9.999u -310.975n -8.593n -258.649p -43.910p -34.610p -29.748p -25.110p -20.906p -16.971p -13.050p -9.130p -5.210p -1.291p 2.628p 10.466p 14.384p DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-7 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.10V 3.20V 3.30V | [POWER_clamp] | |Voltage | 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V 23.157p 27.297p 31.436p 35.576p 39.715p 43.855p 47.995p 56.277p 60.418p 64.561p 68.706p 72.847p 76.869p 80.074p 82.499p 84.837p 89.018p 89.573p 103.108p 372.250p 404.143p 436.027p 467.910p 499.805p 531.722p 563.675p 627.761p 659.933p 692.106p 723.142p 751.973p 780.264p 808.442p 835.513p 860.391p 1.265n 1.305n 1.593n 18.302p 22.221p 26.139p 30.057p 33.974p 37.892p 41.810p 49.646p 53.564p 57.482p 61.400p 65.319p 69.237p 73.156p 77.065p 80.794p 86.195p 88.344p 90.478p I(typ) -33.685p -72.583p -964.564p -20.874n -432.304n -8.033u -85.877u -2.254m -16.024m -55.636m -116.756m -187.395m -262.067m -338.839m -416.878m -495.760m -655.171m -735.446m -815.997m -896.773m -977.735m -1.059 -1.140 -1.221 -1.303 -1.466 -1.548 -1.630 -1.711 -1.793 -1.875 I(min) -340.944n -3.576u -33.637u -295.354u -2.883m -14.319m -37.029m -106.839m -146.891m -188.327m -230.618m -273.482m -316.758m -360.342m -404.164m -448.177m -536.642m -581.048m -625.548m -670.127m -714.777m -759.489m -804.256m -849.071m -893.931m -983.765m -1.029 -1.074 -1.119 -1.164 -1.209 I(max) -20.906p -25.110p -29.748p -34.610p -43.910p -258.649p -8.593n -9.999u -147.930u -845.181u -2.370m -6.612m -33.199m -95.231m -175.533m -262.384m -443.730m -536.295m -629.587m -723.409m -817.634m -912.174m -1.007 -1.102 -1.197 -1.388 -1.483 -1.579 -1.675 -1.771 -1.867 DSP56364 Technical Data, Rev. 4 A-8 Freescale Semiconductor | [Ramp] |Voltage I(typ) I(min) I(max) | dV/dt_f 2.04/136.004p 1.86/237.542p 2.23/85.504p | dV/dt_r 2.05/194.744p 1.86/343.805p 2.23/118.850p R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [Model] ipad5i_io | "" Model_type I/O Vinl = 0.8 Vinh = 2 | variable typ min max C_comp 4.44p 3.89p 4.56p | variable typ min max [Temperature Range] 40.0 0.0 120.0 | variable typ min max [Voltage Range] 3.30V 3.00V 3.60V | [Pulldown] | pulldown in the table = pulldown subtract gnd_clamp |Voltage I(typ) I(min) I(max) | -3.30V -142.303u -76.239u -215.182u -3.20V -149.700u -80.226u -226.432u -3.10V -157.861u -84.616u -238.866u -3.00V -166.908u -89.472u -252.678u -2.90V -176.992u -94.869u -268.107u -2.80V -188.295u -100.900u -285.446u -2.70V -201.049u -107.679u -305.068u -2.60V -215.545u -115.349u -327.446u -2.50V -232.155u -124.094u -353.191u -2.40V -251.367u -134.145u -383.107u -2.30V -273.825u -145.808u -418.273u -2.20V -300.403u -159.488u -460.167u -2.10V -332.314u -175.737u -510.874u -2.00V -371.286u -195.318u -573.418u -1.90V -419.868u -219.325u -652.360u -1.80V -481.968u -249.369u -754.892u -1.70V -563.882u -287.925u -893.013u -1.60V -676.382u -338.973u -1.088m -1.50V -839.410u -409.300u -1.383m -1.40V -1.094m -511.367u -1.873m -1.30V -1.537m -670.350u -2.819m -1.20V -2.451m -943.845u -5.162m -1.10V -4.857m -1.486m -12.214m -1.00V -10.606m -2.746m -20.764m -0.90V -14.267m -5.259m -21.749m -0.80V -13.851m -7.108m -20.142m -0.70V -12.481m -7.168m -18.211m -0.60V -10.883m -6.348m -15.981m -0.50V -9.156m -5.339m -13.503m DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-9 -0.40V -0.30V -0.20V -0.10V 0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.00V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.00V 3.10V 3.20V 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.00V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.00V -7.378m -5.572m -3.741m -1.885m 1.898p 1.857m 3.630m 5.323m 6.936m 8.467m 9.915m 11.275m 12.546m 13.723m 36.925m 39.391m 41.612m 43.585m 45.305m 46.773m 47.997m 48.985m 49.733m 50.257m 50.612m 50.858m 51.040m 51.182m 51.302m 51.405m 51.497m 51.581m 51.658m 51.729m 51.781m 51.640m 50.282m 50.273m 51.871m 55.121m 57.228m 58.838m 60.328m 61.725m 63.035m 64.321m 65.602m 66.844m 68.012m 69.088m 70.072m 70.973m 71.794m 72.529m 73.152m -4.288m -3.224m -2.154m -1.080m 1.419p 1.057m 2.064m 3.023m 3.935m 4.798m 5.611m 6.371m 7.078m 7.726m 20.745m 22.074m 23.244m 24.247m 25.079m 25.741m 26.251m 26.633m 26.905m 27.092m 27.223m 27.321m 27.399m 27.465m 27.522m 27.572m 27.618m 27.658m 27.683m 27.643m 27.704m 28.793m 30.065m 31.174m 32.200m 33.153m 34.039m 34.872m 35.687m 36.498m 37.296m 38.059m 38.767m 39.409m 39.982m 40.478m 40.871m 41.102m 40.996m 40.118m 39.453m -10.922m -8.282m -5.584m -2.825m 1.871p 2.800m 5.482m 8.052m 10.508m 12.849m 15.073m 17.176m 19.155m 21.011m 56.704m 60.708m 64.383m 67.726m 70.735m 73.414m 75.766m 77.783m 79.441m 80.724m 81.651m 82.294m 82.744m 83.074m 83.332m 83.543m 83.724m 83.884m 84.030m 84.165m 84.290m 84.409m 84.519m 84.574m 83.365m 80.948m 81.423m 83.424m 87.158m 91.951m 94.228m 96.276m 98.249m 100.060m 101.853m 103.638m 105.361m 106.982m 108.484m 109.875m 111.168m DSP56364 Technical Data, Rev. 4 A-10 Freescale Semiconductor 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.00V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V 73.605m 73.737m 72.999m 71.115m 70.512m 70.457m 70.511m 70.586m 70.667m 70.749m 70.831m 70.911m 70.989m 71.068m 71.148m 71.230m 39.379m 39.432m 39.492m 39.551m 39.608m 39.661m 39.713m 39.762m 39.809m 39.855m 39.899m 39.944m 39.988m 40.034m 40.083m 40.136m 112.374m 113.492m 114.510m 115.392m 116.061m 116.301m 114.763m 111.545m 110.833m 110.689m 110.716m 110.796m 110.897m 111.009m 111.127m 111.250m | [Pullup] | pullup in the table = pullup subtract power_clamp |Voltage I(typ) I(min) I(max) | -3.30V 357.190u 184.381u 591.381u -3.20V 356.622u 184.121u 590.188u -3.10V 356.193u 183.920u 589.287u -3.00V 355.875u 183.765u 588.617u -2.90V 355.641u 183.645u 588.129u -2.80V 355.468u 183.550u 587.779u -2.70V 355.340u 183.472u 587.528u -2.60V 355.242u 183.405u 587.349u -2.50V 355.163u 183.345u 587.218u -2.40V 355.097u 183.288u 587.118u -2.30V 355.036u 183.233u 587.036u -2.20V 354.978u 183.177u 586.964u -2.10V 354.920u 183.119u 586.896u -2.00V 354.860u 183.060u 586.829u -1.90V 354.799u 182.997u 586.762u -1.80V 354.734u 182.931u 586.692u -1.70V 354.666u 182.862u 586.621u -1.60V 354.595u 182.788u 586.574u -1.50V 354.559u 182.711u 597.934u -1.40V 764.198u 182.650u 1.674m -1.30V 10.536m 460.815u 14.880m -1.20V 9.648m 6.455m 13.612m -1.10V 8.683m 5.841m 12.257m -1.00V 7.701m 5.195m 10.870m -0.90V 6.737m 4.554m 9.492m -0.80V 5.827m 3.944m 8.173m -0.70V 5.004m 3.383m 6.972m -0.60V 4.262m 2.870m 5.921m -0.50V 3.549m 2.382m 4.953m -0.40V 2.841m 1.902m 3.978m -0.30V 2.134m 1.426m 2.985m -0.20V 1.434m 951.249u 2.002m -0.10V 721.882u 477.946u 1.005m -0.00V 23.094p 36.805p 24.891p DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-11 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.00V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.00V 3.10V 3.20V 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.00V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.00V 5.10V 5.20V 5.30V 5.40V 5.50V -708.040u -465.659u -990.277u -1.374m -903.549u -1.941m -2.007m -1.319m -2.832m -2.614m -1.710m -3.702m -3.192m -2.079m -4.537m -3.738m -2.423m -5.336m -4.253m -2.742m -6.096m -4.736m -3.037m -6.817m -5.185m -3.305m -7.499m -5.600m -3.547m -8.139m -5.980m -3.762m -8.737m -6.324m -3.948m -9.292m -6.631m -17.709m -9.802m -29.730m -18.279m -10.265m -30.749m -18.747m -45.983m -31.630m -19.131m -47.620m -32.393m -19.454m -49.086m -33.055m -19.730m -50.392m -33.632m -19.973m -51.551m -34.135m -20.188m -52.571m -34.575m -20.381m -53.463m -34.960m -20.556m -54.240m -35.302m -20.715m -54.917m -35.608m -20.861m -55.510m -35.884m -20.997m -56.035m -36.137m -21.123m -56.505m -36.370m -21.241m -56.932m -36.586m -21.352m -57.322m -36.788m -21.457m -57.683m -36.978m -21.556m -58.019m -37.157m -21.650m -58.334m -37.327m -21.741m -58.631m -37.489m -21.827m -58.913m -37.643m -21.909m -59.181m -37.791m -21.989m -59.436m -37.933m -22.067m -59.681m -38.070m -22.143m -59.916m -38.202m -22.216m -60.142m -38.332m -22.284m -60.361m -38.460m -22.352m -60.573m -38.590m -22.420m -60.780m -38.714m -22.490m -60.986m -38.828m -22.561m -61.194m -38.949m -22.635m -61.406m -39.076m -22.713m -61.623m -39.211m -22.798m -61.819m -39.357m -22.892m -62.024m -39.516m -22.997m -62.254m -39.693m -23.116m -62.506m -39.893m -23.253m -62.785m -40.121m -23.411m -63.098m -40.384m -23.595m -63.453m -40.689m -23.801m -63.860m -41.043m -24.032m -64.330m -41.444m -24.288m -64.874m DSP56364 Technical Data, Rev. 4 A-12 Freescale Semiconductor 5.60V 5.70V 5.80V 5.90V 6.00V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V | [GND_clamp] | |Voltage | -3.30V -3.20V -3.10V -2.90V -2.80V -2.70V -2.60V -2.50V -2.40V -2.30V -2.20V -2.10V -1.90V -1.80V -1.70V -1.60V -1.50V -1.40V -1.30V -1.20V -1.10V -0.90V -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V 0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V -41.886m -42.370m -42.899m -43.473m -44.095m -44.769m -45.498m -46.287m -47.140m -48.049m -48.990m -24.570m -24.880m -25.217m -25.585m -25.983m -26.415m -26.884m -27.390m -27.929m -28.487m -29.080m -65.505m -66.214m -66.983m -67.815m -68.711m -69.678m -70.721m -71.848m -73.065m -74.374m -75.748m I(typ) -1.875 -1.793 -1.711 -1.548 -1.466 -1.385 -1.303 -1.221 -1.140 -1.059 -977.740m -896.779m -735.452m -655.177m -575.247m -495.766m -416.883m -338.844m -262.072m -187.399m -116.760m -16.027m -2.255m -476.049u -85.878u -8.033u -432.308n -20.878n -968.068p -75.987p -36.990p -30.869p -25.858p -21.307p -17.033p -12.783p -8.537p -4.293p -49.635f I(min) -1.074 -1.029 -983.769m -893.934m -849.075m -804.259m -759.493m -714.781m -670.131m -625.551m -581.052m -536.646m -448.180m -404.167m -360.345m -316.761m -273.485m -230.621m -188.330m -146.893m -106.842m -37.031m -14.321m -2.884m -295.501u -33.646u -3.576u -340.971n -30.900n -2.564n -214.009p -34.018p 10.263p 45.181p 78.801p 111.888p 144.645p 177.177p 209.548p I(max) -2.155 -2.059 -1.963 -1.771 -1.675 -1.579 -1.483 -1.388 -1.292 -1.197 -1.102 -1.007 -817.639m -723.415m -629.593m -536.300m -443.735m -352.227m -262.388m -175.537m -95.235m -6.614m -2.370m -845.183u -147.930u -9.999u -310.979n -8.597n -262.449p -47.610p -38.210p -33.249p -28.510p -24.206p -20.171p -16.150p -12.130p -8.110p -4.091p DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-13 0.90V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.10V 3.20V 3.30V | [POWER_clamp] | |Voltage | 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.10V 6.20V 6.30V 4.192p 12.674p 16.914p 21.154p 25.393p 29.633p -31.788p 38.112p 42.352p 46.592p 55.074p 59.316p 63.559p 67.803p 72.044p 76.162p 79.409p 81.838p 84.178p 88.733p 90.025p 96.129p 241.802p 306.070p 338.124p 370.146p 402.147p 434.138p 466.129p 498.131p 530.156p 562.217p 626.519p 658.799p 691.080p 722.224p 751.129p 779.443p 807.731p 835.534p 864.770p 1.234n 1.247n 1.274n -71.907f 7.965p 11.984p 16.002p 20.020p 24.038p 28.056p -33.622p 36.092p 40.110p 48.146p 52.164p 56.182p 60.200p 64.219p 68.237p 72.256p 76.265p 80.080p 85.501p 87.652p 89.793p I(typ) -36.990p -75.987p -968.068p -20.878n -432.308n -8.033u -85.878u -2.255m -16.027m -55.640m -116.760m -187.399m -262.072m -338.844m -416.883m -495.766m -655.177m -735.452m -816.003m -896.779m -977.740m -1.059 -1.140 -1.221 -1.303 -1.466 -1.548 -1.630 I(min) -340.971n -3.576u -33.646u -295.501u -2.884m -14.321m -37.031m -106.842m -146.893m -188.330m -230.621m -273.485m -316.761m -360.345m -404.167m -448.180m -536.646m -581.052m -625.551m -670.131m -714.781m -759.493m -804.259m -849.075m -893.934m -983.769m -1.029 -1.074 I(max) -24.206p -28.510p -33.249p -38.210p -47.610p -262.449p -8.597n -9.999u -147.930u -845.183u -2.370m -6.614m -33.203m -95.235m -175.537m -262.388m -443.735m -536.300m -629.593m -723.415m -817.639m -912.179m -1.007 -1.102 -1.197 -1.388 -1.483 -1.579 DSP56364 Technical Data, Rev. 4 A-14 Freescale Semiconductor 6.40V 6.50V 6.60V -1.711 -1.793 -1.875 -1.119 -1.164 -1.209 -1.675 -1.771 -1.867 | [Ramp] |Voltage I(typ) I(min) I(max) | dV/dt_f 2.01/129.093p 1.83/223.594p 2.20/79.668p | dV/dt_r 2.02/200.492p 1.83/352.515p 2.20/122.321p R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [Model] ipad5v_io | "" Model_type I/O Vinl = 0.8 Vinh = 2 | variable typ min max C_comp 1.96p 1.87p 2.06p | variable typ min max [Temperature Range] 40.0 0.0 120.0 | variable typ min max [Voltage Range] 3.30V 3.00V 3.60V | [Pulldown] | pulldown in the table = pulldown subtract gnd_clamp |Voltage I(typ) I(min) I(max) | -3.30V -142.303u -76.239u -215.182u -3.20V -149.700u -80.226u -226.432u -3.10V -157.861u -84.616u -238.866u -3.00V -166.908u -89.472u -252.678u -2.90V -176.992u -94.869u -268.107u -2.80V -188.295u -100.900u -285.446u -2.70V -201.049u -107.679u -305.068u -2.60V -215.545u -115.349u -327.446u -2.50V -232.155u -124.094u -353.191u -2.40V -251.367u -134.145u -383.107u -2.30V -273.825u -145.808u -418.273u -2.20V -300.403u -159.488u -460.167u -2.10V -332.314u -175.737u -510.874u -2.00V -371.286u -195.318u -573.418u -1.90V -419.868u -219.325u -652.360u -1.80V -481.968u -249.369u -754.892u -1.70V -563.882u -287.925u -893.013u -1.60V -676.382u -338.973u -1.088m -1.50V -839.410u -409.300u -1.383m -1.40V -1.094m -511.367u -1.873m -1.30V -1.537m -670.350u -2.819m -1.20V -2.451m -943.845u -5.162m -1.10V -4.857m -1.486m -12.214m -1.00V -10.606m -2.746m -20.764m -0.90V -14.267m -5.259m -21.749m -0.80V -13.851m -7.108m -20.142m DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-15 -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V 0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.00V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.00V 3.10V 3.20V 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.00V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V -12.481m -10.883m -9.156m -7.378m -5.572m -3.741m -1.885m 1.898p 1.857m 3.630m 5.323m 6.936m 8.467m 9.915m 11.275m 12.546m 13.723m 36.925m 39.391m 41.612m 43.585m 45.305m 46.773m 47.997m 48.985m 49.733m 50.257m 50.612m 50.858m 51.040m 51.182m 51.302m 51.405m 51.497m 51.581m 51.658m 51.727m 51.757m 51.229m 49.190m 49.441m 51.034m 54.363m 57.165m 58.834m 60.328m 61.725m 63.035m 64.319m 65.598m 66.836m 67.999m 69.069m 70.046m 70.938m -7.168m -6.348m -5.339m -4.288m -3.224m -2.154m -1.080m 1.419p 1.057m 2.064m 3.023m 3.935m 4.798m 5.611m 6.371m 7.078m 7.726m 20.745m 22.074m 23.244m 24.247m 25.079m 25.741m 26.251m 26.633m 26.905m 27.092m 27.223m 27.321m 27.399m 27.465m 27.522m 27.572m 27.618m 27.657m 27.674m 27.587m 27.577m 28.700m 30.042m 31.171m 32.199m 33.153m 34.039m 34.872m 35.686m 36.495m 37.291m 38.051m 38.755m 39.394m 39.962m 40.453m 40.840m 41.065m -18.211m -15.981m -13.503m -10.922m -8.282m -5.584m -2.825m 1.871p 2.800m 5.482m 8.052m 10.508m 12.849m 15.073m 17.176m 19.155m 21.011m 56.704m 60.708m 64.383m 67.726m 70.735m 73.414m 75.766m 77.783m 79.441m 80.724m 81.651m 82.294m 82.744m 83.074m 83.332m 83.543m 83.724m 83.884m 84.030m 84.165m 84.290m 84.409m 84.515m 84.491m 81.077m 79.736m 80.276m 82.430m 85.482m 91.743m 94.219m 96.276m 98.249m 100.059m 101.849m 103.628m 105.345m 106.956m DSP56364 Technical Data, Rev. 4 A-16 Freescale Semiconductor 4.80V 4.90V 5.00V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.00V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V 71.751m 72.476m 73.089m 73.531m 73.651m 72.901m 71.005m 70.389m 70.321m 70.361m 70.422m 70.489m 70.557m 70.624m 70.690m 70.753m 70.817m 70.881m 70.949m 40.952m 40.067m 39.395m 39.313m 39.358m 39.410m 39.460m 39.508m 39.552m 39.595m 39.634m 39.672m 39.708m 39.743m 39.777m 39.812m 39.848m 39.886m 39.929m 108.448m 109.826m 111.106m 112.297m 113.400m 114.401m 115.267m 115.917m 116.139m 114.582m 111.344m 110.612m 110.449m 110.455m 110.515m 110.595m 110.686m 110.783m 110.885m | [Pullup] | pullup in the table = pullup subtract power_clamp |Voltage I(typ) I(min) I(max) | -3.30V 75.797u 7.914u 161.477u -3.20V 90.464u 17.699u 181.779u -3.10V 105.160u 27.445u 202.314u -3.00V 119.836u 37.119u 223.007u -2.90V 134.451u 46.694u 243.785u -2.80V 148.966u 56.144u 264.581u -2.70V 163.342u 65.447u 285.332u -2.60V 177.543u 74.582u 305.982u -2.50V 191.536u 83.527u 326.474u -2.40V 205.285u 92.262u 346.757u -2.30V 218.754u 100.766u 366.776u -2.20V 231.907u 109.016u 386.478u -2.10V 244.706u 116.988u 405.807u -2.00V 257.106u 124.659u 424.699u -1.90V 269.061u 131.998u 443.089u -1.80V 280.519u 138.978u 460.899u -1.70V 291.423u 145.565u 478.046u -1.60V 301.710u 151.723u 494.457u -1.50V 311.348u 157.417u 521.406u -1.40V 729.899u 162.626u 1.612m -1.30V 10.510m 445.517u 14.832m -1.20V 9.629m 6.444m 13.576m -1.10V 8.670m 5.833m 12.231m -1.00V 7.693m 5.190m 10.854m -0.90V 6.732m 4.551m 9.483m -0.80V 5.825m 3.942m 8.169m -0.70V 5.004m 3.382m 6.971m -0.60V 4.261m 2.869m 5.921m -0.50V 3.549m 2.381m 4.953m DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-17 -0.40V -0.30V -0.20V -0.10V -0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.00V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.00V 3.10V 3.20V 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.00V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.00V 2.841m 1.902m 3.978m 2.135m 1.426m 2.987m 1.437m 951.489u 2.003m 722.340u 478.341u 1.005m 22.329p 36.936p 24.081p -708.556u -465.927u -990.647u -1.377m -903.637u -1.943m -2.007m -1.319m -2.832m -2.614m -1.710m -3.702m -3.192m -2.079m -4.537m -3.738m -2.423m -5.336m -4.253m -2.742m -6.096m -4.736m -3.037m -6.817m -5.185m -3.305m -7.499m -5.600m -3.547m -8.139m -5.980m -3.762m -8.737m -6.324m -3.948m -9.292m -6.631m -17.709m -9.802m -29.730m -18.279m -10.265m -30.749m -18.747m -45.983m -31.630m -19.131m -47.620m -32.393m -19.454m -49.086m -33.055m -19.730m -50.392m -33.632m -19.973m -51.551m -34.135m -20.188m -52.571m -34.575m -20.381m -53.463m -34.960m -20.556m -54.240m -35.302m -20.715m -54.917m -35.608m -20.861m -55.510m -35.884m -20.997m -56.035m -36.137m -21.123m -56.505m -36.370m -21.241m -56.932m -36.586m -21.352m -57.322m -36.788m -21.457m -57.683m -36.978m -21.556m -58.019m -37.157m -21.650m -58.334m -37.327m -21.741m -58.631m -37.489m -21.827m -58.913m -37.643m -21.909m -59.181m -37.791m -21.989m -59.436m -37.933m -22.067m -59.681m -38.070m -22.143m -59.916m -38.202m -22.216m -60.142m -38.332m -22.284m -60.361m -38.460m -22.352m -60.573m -38.590m -22.420m -60.780m -38.714m -22.490m -60.986m -38.828m -22.561m -61.194m -38.949m -22.635m -61.406m -39.076m -22.713m -61.623m -39.211m -22.798m -61.819m -39.357m -22.892m -62.024m -39.516m -22.997m -62.254m -39.693m -23.116m -62.506m -39.893m -23.253m -62.785m DSP56364 Technical Data, Rev. 4 A-18 Freescale Semiconductor 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.00V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V | [GND_clamp] | |Voltage | -3.30V -3.20V -3.10V -2.90V -2.80V -2.70V -2.60V -2.50V -2.40V -2.30V -2.20V -2.10V -1.90V -1.80V -1.70V -1.60V -1.50V -1.40V -1.30V -1.20V -1.10V -0.90V -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V 0.00V 0.10V 0.20V 0.30V -40.121m -40.384m -40.689m -41.043m -41.444m -41.886m -42.370m -42.899m -43.473m -44.095m -44.769m -45.498m -46.287m -47.140m -48.049m -48.990m -23.411m -23.595m -23.801m -24.032m -24.288m -24.570m -24.880m -25.217m -25.585m -25.983m -26.415m -26.884m -27.390m -27.929m -28.487m -29.080m -63.098m -63.453m -63.860m -64.330m -64.874m -65.505m -66.214m -66.983m -67.815m -68.711m -69.678m -70.721m -71.848m -73.065m -74.374m -75.748m I(typ) -1.875 -1.793 -1.711 -1.548 -1.466 -1.385 -1.303 -1.221 -1.140 -1.059 -977.735m -896.773m -735.446m -655.171m -575.242m -495.760m -416.878m -338.839m -262.067m -187.395m -116.756m -16.024m -2.254m -476.015u -85.877u -8.033u -432.304n -20.874n -964.564p -72.583p -33.685p -27.665p -22.754p -18.303p I(min) -1.074 -1.029 -983.765m -893.931m -849.071m -804.256m -759.489m -714.777m -670.127m -625.548m -581.048m -536.642m -448.177m -404.164m -360.342m -316.758m -273.482m -230.618m -188.327m -146.891m -106.839m -37.029m -14.319m -2.883m -295.354u -33.637u -3.576u -340.944n -30.895n -2.560n -210.508p -30.628p 13.546p 48.356p I(max) -2.155 -2.059 -1.963 -1.771 -1.675 -1.579 -1.483 -1.388 -1.292 -1.197 -1.102 -1.007 -817.634m -723.409m -629.587m -536.295m -443.730m -352.222m -262.384m -175.533m -95.231m -6.612m -2.370m -845.181u -147.930u -9.999u -310.975n -8.593n -258.649p -43.910p -34.610p -29.748p -25.110p -20.906p DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-19 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.10V 3.20V 3.30V | [POWER_clamp] | |Voltage | 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V -14.129p -9.979p -5.833p -1.689p 2.454p 6.596p 14.877p 19.017p 23.157p 27.297p 31.436p 35.576p 39.715p 43.855p 47.995p 56.277p 60.418p 64.561p 68.706p 72.847p 76.869p 80.074p 82.499p 84.837p 89.018p 89.573p 103.108p 81.869p 114.849p 147.499p 179.924p 212.188p 244.335p 308.388p 340.335p 372.250p 404.143p 436.027p 467.910p 499.805p 531.722p 563.675p 627.761p 659.933p 692.106p 723.142p 751.973p 780.264p 808.442p 835.513p 860.391p 1.265n 1.305n 1.593n -16.971p -13.050p -9.130p -5.210p -1.291p 2.628p 10.466p 14.384p 18.302p 22.221p 26.139p 30.057p 33.974p 37.892p 41.810p 49.646p 53.564p 57.482p 61.400p 65.319p 69.237p 73.156p 77.065p 80.794p 86.195p 88.344p 90.478p I(typ) -33.685p -72.583p -964.564p -20.874n -432.304n -8.033u -85.877u -2.254m -16.024m -55.636m -116.756m -187.395m -262.067m -338.839m -416.878m -495.760m -655.171m -735.446m -815.997m -896.773m -977.735m -1.059 -1.140 I(min) -340.944n -3.576u -33.637u -295.354u -2.883m -14.319m -37.029m -106.839m -146.891m -188.327m -230.618m -273.482m -316.758m -360.342m -404.164m -448.177m -536.642m -581.048m -625.548m -670.127m -714.777m -759.489m -804.256m I(max) -20.906p -25.110p -29.748p -34.610p -43.910p -258.649p -8.593n -9.999u -147.930u -845.181u -2.370m -6.612m -33.199m -95.231m -175.533m -262.384m -443.730m -536.295m -629.587m -723.409m -817.634m -912.174m -1.007 DSP56364 Technical Data, Rev. 4 A-20 Freescale Semiconductor 5.80V 5.90V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V -1.221 -849.071m -1.303 -893.931m -1.466 -983.765m -1.548 -1.029 -1.630 -1.074 -1.711 -1.119 -1.793 -1.164 -1.875 -1.209 -1.102 -1.197 -1.388 -1.483 -1.579 -1.675 -1.771 -1.867 | [Ramp] |Voltage I(typ) I(min) I(max) | dV/dt_f 2.04/134.002p 1.86/235.405p 2.23/85.874p | dV/dt_r 2.05/194.838p 1.86/341.412p 2.23/118.822p R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [Model] ipada_3st | "" Model_type 3-state | variable typ min max C_comp 2.32p 2.17p 2.48p | variable typ min max [Temperature Range] 40.0 0.0 120.0 | variable typ min max [Voltage Range] 3.30V 3.00V 3.60V | [Pulldown] | pulldown in the table = pulldown subtract gnd_clamp |Voltage I(typ) I(min) I(max) | -3.30V -157.134u -99.256u -219.000u -3.20V -165.037u -104.127u -230.250u -3.10V -173.749u -109.479u -242.685u -3.00V -183.400u -115.386u -256.500u -2.90V -194.148u -121.936u -271.934u -2.80V -206.189u -129.240u -289.286u -2.70V -219.766u -137.431u -308.933u -2.60V -235.190u -146.680u -331.355u -2.50V -252.856u -157.199u -357.176u -2.40V -273.283u -169.265u -387.219u -2.30V -297.162u -183.236u -422.595u -2.20V -325.427u -199.590u -464.837u -2.10V -359.384u -218.976u -516.117u -2.00V -400.901u -242.299u -579.623u -1.90V -452.750u -270.851u -660.217u -1.80V -519.217u -306.549u -765.681u -1.70V -607.277u -352.346u -909.270u -1.60V -729.045u -413.024u -1.115m -1.50V -907.407u -496.811u -1.434m -1.40V -1.191m -619.011u -1.987m -1.30V -1.699m -811.079u -3.133m -1.20V -2.799m -1.146m -6.243m -1.10V -5.689m -1.822m -12.974m DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-21 -1.00V -0.90V -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V 0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.00V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.00V 3.10V 3.20V 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.00V 4.10V 4.20V 4.30V 4.40V -10.416m -3.302m -12.342m -5.449m -11.672m -6.479m -10.528m -6.146m -9.204m -5.387m -7.770m -4.535m -6.286m -3.652m -4.766m -2.754m -3.214m -1.846m -1.627m -928.990u 32.871e-18 18.541e-18 1.604m 910.814u 3.124m 1.775m 4.566m 2.595m 5.928m 3.372m 7.210m 4.105m 8.411m 4.792m 9.529m 5.432m 10.562m 6.023m 11.508m 6.563m 12.367m 7.051m 13.138m 7.486m 13.821m 7.865m 14.417m 8.189m 14.930m 64.562m 117.094m 66.208m 119.708m 67.513m 121.667m 68.498m 123.055m 69.206m 124.020m 69.710m 124.711m 70.083m 125.232m 70.374m 125.650m 70.612m 126.000m 70.814m 126.305m 70.992m 126.577m 71.151m 126.823m 71.296m 127.050m 71.428m 127.260m 71.551m 127.457m 71.666m 127.643m 71.774m 127.818m 71.876m 127.986m 71.973m 128.147m 72.066m 128.304m 72.156m 128.458m 72.245m 128.614m 72.335m 128.776m 72.428m 128.948m 72.527m 129.140m 72.638m 129.361m 72.764m 129.621m 72.914m 129.934m 73.093m 130.316m 73.311m 130.784m 73.579m -17.948m -17.964m -16.692m -15.152m -13.338m -11.313m -9.190m -6.999m -4.740m -2.410m -1.607f 2.391m 4.661m 6.817m 8.858m 10.784m 12.593m 14.284m 15.855m 17.306m 18.639m 19.856m 20.957m 21.944m 22.817m 23.575m 184.138m 187.874m 190.647m 192.621m 194.017m 195.034m 195.815m 196.447m 196.983m 197.453m 197.876m 198.263m 198.622m 198.958m 199.275m 199.576m 199.863m 200.138m 200.405m 200.667m 200.928m 201.194m 201.472m 201.774m 202.113m 202.503m 202.966m 203.524m 204.203m DSP56364 Technical Data, Rev. 4 A-22 Freescale Semiconductor 4.50V 4.60V 4.70V 4.80V 4.90V 5.00V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.00V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V 131.358m 132.060m 132.912m 133.939m 135.166m 136.619m 138.324m 140.308m 142.597m 145.217m 148.192m 151.545m 155.300m 159.478m 164.097m 169.177m 174.734m 180.781m 187.333m 194.400m 201.993m 210.118m 73.906m 74.304m 74.787m 75.368m 76.060m 76.878m 77.836m 78.948m 80.230m 81.694m 83.355m 85.224m 87.316m 89.640m 92.208m 95.029m 98.112m 101.465m 105.096m 109.009m 113.211m 117.705m 205.033m 206.045m 207.276m 208.763m 210.544m 212.659m 215.149m 218.056m 221.419m 225.277m 229.669m 234.630m 240.194m 246.393m 253.255m 260.806m 269.070m 278.065m 287.810m 298.319m 309.602m 321.670m | [Pullup] | pullup in the table = pullup subtract power_clamp |Voltage I(typ) I(min) I(max) | -3.30V 132.979u 100.794u 170.075u -3.20V 138.984u 105.115u 178.000u -3.10V 145.559u 109.825u 186.702u -3.00V 152.789u 114.981u 196.300u -2.90V 160.778u 120.648u 206.941u -2.80V 169.651u 126.906u 218.803u -2.70V 179.562u 133.852u 232.110u -2.60V 190.706u 141.605u 247.141u -2.50V 203.326u 150.317u 264.253u -2.40V 217.736u 160.174u 283.910u -2.30V 234.344u 171.418u 306.723u -2.20V 253.692u 184.362u 333.513u -2.10V 276.513u 199.421u 365.415u -2.00V 303.830u 217.155u 404.033u -1.90V 337.102u 238.340u 451.722u -1.80V 378.494u 264.081u 512.067u -1.70V 431.351u 296.004u 590.810u -1.60V 501.113u 336.601u 697.730u -1.50V 597.240u 389.880u 850.877u -1.40V 737.641u 462.700u 1.087m -1.30V 960.395u 567.748u 1.497m -1.20V 1.361m 731.012u 2.348m -1.10V 2.237m 1.013m 4.712m -1.00V 4.644m 1.583m 10.148m -0.90V 8.090m 2.907m 12.062m -0.80V 8.032m 4.727m 11.029m -0.70V 7.118m 4.754m 9.778m -0.60V 6.128m 4.128m 8.443m DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-23 -0.50V -0.40V -0.30V -0.20V -0.10V -0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.00V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.00V 3.10V 3.20V 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.00V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.109m 3.441m 7.052m 4.082m 2.746m 5.644m 3.056m 2.053m 4.233m 2.033m 1.363m 2.821m 1.014m 678.856u 1.410m 58.687e-18 58.622e-18 117.504e-18 -987.106u -655.604u -1.381m -1.928m -1.274m -2.709m -2.828m -1.859m -3.988m -3.685m -2.412m -5.216m -4.499m -2.931m -6.392m -5.269m -3.416m -7.516m -5.994m -3.866m -8.587m -6.673m -4.280m -9.602m -7.306m -4.658m -10.561m -7.890m -4.999m -11.461m -8.424m -5.301m -12.302m -8.907m -5.563m -13.081m -9.339m -65.539m -13.798m -110.103m -67.611m -154.438m -113.807m -69.311m -170.370m -117.010m -70.713m -176.323m -119.783m -71.893m -181.647m -122.195m -72.910m -186.387m -124.297m -73.804m -190.581m -126.131m -74.599m -194.261m -127.733m -75.311m -197.468m -129.139m -75.954m -200.255m -130.384m -76.540m -202.683m -131.498m -77.077m -204.814m -132.504m -77.575m -206.704m -133.423m -78.037m -208.399m -134.270m -78.470m -209.937m -135.057m -78.877m -211.346m -135.792m -79.261m -212.650m -136.483m -79.625m -213.864m -137.136m -79.971m -215.004m -137.756m -80.302m -216.079m -138.345m -80.617m -217.098m -138.908m -80.920m -218.067m -139.447m -81.210m -218.993m -139.964m -81.490m -219.880m -140.462m -81.761m -220.732m -140.943m -82.022m -221.552m -141.408m -82.277m -222.344m -141.860m -82.525m -223.112m -142.300m -82.769m -223.858m -142.733m -83.010m -224.586m -143.159m -83.250m -225.300m -143.585m -83.493m -226.006m -144.013m -83.740m -226.709m -144.449m -83.996m -227.417m -144.899m -84.265m -228.137m -145.370m -84.551m -228.879m -145.871m -84.861m -229.656m DSP56364 Technical Data, Rev. 4 A-24 Freescale Semiconductor 5.00V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.00V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V | [GND_clamp] | |Voltage | -3.30V -3.20V -3.10V -2.90V -2.80V -2.70V -2.60V -2.50V -2.40V -2.30V -2.20V -2.10V -1.90V -1.80V -1.70V -1.60V -1.50V -1.40V -1.30V -1.20V -1.10V -0.90V -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V 0.00V 0.10V 0.20V -146.411m -85.200m -147.001m -85.575m -147.652m -85.993m -148.379m -86.464m -149.195m -86.995m -150.115m -87.597m -151.157m -88.280m -152.339m -89.054m -153.678m -89.930m -155.194m -90.921m -156.907m -92.038m -158.839m -93.294m -161.011m -94.701m -163.444m -96.273m -166.160m -98.023m -169.182m -99.963m -172.531m -102.106m -230.481m -231.368m -232.336m -233.404m -234.592m -235.924m -237.426m -239.124m -241.046m -243.223m -245.685m -248.465m -251.595m -255.109m -259.041m -263.425m -268.293m I(typ) -2.637 -2.521 -2.406 -2.174 -2.059 -1.943 -1.828 -1.713 -1.598 -1.483 -1.368 -1.254 -1.026 -912.311m -799.377m -687.103m -575.715m -465.583m -357.354m -252.314m -153.494m -19.457m -3.535m -877.640u -156.838u -14.514u -780.351n -37.668n -1.699n -92.071p -27.709p -22.802p -19.598p I(min) -1.514 -1.451 -1.387 -1.259 -1.195 -1.132 -1.068 -1.004 -941.073m -877.750m -814.544m -751.475m -625.847m -563.357m -501.149m -439.297m -377.904m -317.129m -257.221m -198.614m -142.138m -45.305m -16.226m -3.288m -397.909u -53.601u -6.086u -598.098n -55.739n -5.410n -1.212n -890.771p -810.054p I(max) -3.063 -2.926 -2.789 -2.515 -2.378 -2.242 -2.105 -1.969 -1.833 -1.697 -1.561 -1.425 -1.155 -1.021 -886.904m -753.859m -621.897m -491.519m -363.667m -240.395m -127.373m -11.215m -4.650m -1.613m -271.662u -18.044u -560.308n -15.437n -411.332p -29.683p -18.939p -16.163p -13.516p DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-25 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.10V 3.20V 3.30V | [POWER_clamp] | |Voltage | 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V -16.468p -13.353p -10.247p -7.147p -4.050p -955.896f 2.136p 8.315p 11.404p 14.492p 17.579p 20.666p 23.754p 26.841p 29.929p 33.018p 39.198p 42.291p 45.385p 48.483p 51.583p 54.673p 57.468p 59.647p 61.717p 65.859p 68.003p 72.601p -745.765p -10.874p -683.799p -8.234p -622.802p -5.595p -562.404p -2.956p -502.414p -318.962f -442.712p 2.318p -383.217p 4.954p -264.634p 10.227p -205.467p 12.862p -146.346p 15.498p -87.245p 18.133p -28.141p 20.768p 30.987p 23.404p 90.164p 26.039p 149.414p 28.674p 208.769p 31.310p 327.949p 36.581p 387.873p 39.216p 448.012p 41.852p 507.296p 44.489p 563.856p 47.125p 619.785p 49.762p 676.156p 52.401p 733.868p 55.040p 807.258p 57.675p 5.906n 61.928p 59.801n 63.585p 620.266n 65.236p I(typ) -27.709p -92.071p -1.699n -37.668n -780.351n -14.514u -156.838u -3.535m -19.457m -69.631m -153.494m -252.314m -357.354m -465.583m -575.715m -687.103m -912.311m -1.026 -1.140 -1.254 -1.368 -1.483 I(min) -598.098n -6.086u -53.601u -397.909u -3.288m -16.226m -45.305m -142.138m -198.614m -257.221m -317.129m -377.904m -439.297m -501.149m -563.357m -625.847m -751.475m -814.544m -877.750m -941.073m -1.004 -1.068 I(max) -10.874p -13.516p -16.163p -18.939p -29.683p -411.332p -15.437n -18.044u -271.662u -1.613m -4.650m -11.215m -43.562m -127.373m -240.395m -363.667m -621.897m -753.859m -886.904m -1.021 -1.155 -1.290 DSP56364 Technical Data, Rev. 4 A-26 Freescale Semiconductor 5.70V 5.80V 5.90V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V -1.598 -1.713 -1.828 -2.059 -2.174 -2.290 -2.406 -2.521 -2.637 -1.132 -1.195 -1.259 -1.387 -1.451 -1.514 -1.578 -1.642 -1.706 -1.425 -1.561 -1.697 -1.969 -2.105 -2.242 -2.378 -2.515 -2.652 | [Ramp] |Voltage I(typ) I(min) I(max) | dV/dt_f 1.99/110.010p 1.81/184.463p 2.17/69.974p | dV/dt_r 2.04/120.172p 1.85/212.126p 2.21/73.179p R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [Model] ipadd_io | "" Model_type I/O Vinl = 0.8 Vinh = 2 | variable typ min max C_comp 2.34p 2.21p 2.52p | variable typ min max [Temperature Range] 40.0 0.0 120.0 | variable typ min max [Voltage Range] 3.30V 3.00V 3.60V | [Pulldown] | pulldown in the table = pulldown subtract gnd_clamp |Voltage I(typ) I(min) I(max) | -3.30V -157.134u -99.256u -219.000u -3.20V -165.037u -104.127u -230.250u -3.10V -173.749u -109.479u -242.685u -3.00V -183.400u -115.386u -256.500u -2.90V -194.148u -121.936u -271.934u -2.80V -206.189u -129.240u -289.286u -2.70V -219.766u -137.431u -308.933u -2.60V -235.190u -146.680u -331.355u -2.50V -252.856u -157.199u -357.176u -2.40V -273.283u -169.265u -387.219u -2.30V -297.162u -183.236u -422.595u -2.20V -325.427u -199.590u -464.837u -2.10V -359.384u -218.976u -516.117u -2.00V -400.901u -242.299u -579.623u -1.90V -452.750u -270.851u -660.217u -1.80V -519.217u -306.549u -765.681u -1.70V -607.277u -352.346u -909.270u -1.60V -729.045u -413.024u -1.115m -1.50V -907.407u -496.811u -1.434m -1.40V -1.191m -619.011u -1.987m DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-27 -1.30V -1.20V -1.10V -1.00V -0.90V -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V 0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.00V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.00V 3.10V 3.20V 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.00V 4.10V -1.699m -811.079u -2.799m -1.146m -5.689m -1.822m -10.416m -3.302m -12.342m -5.449m -11.672m -6.479m -10.528m -6.146m -9.204m -5.387m -7.770m -4.535m -6.286m -3.652m -4.766m -2.754m -3.214m -1.846m -1.627m -928.990u 32.871e-18 18.540e-18 1.604m 910.814u 3.124m 1.775m 4.566m 2.595m 5.928m 3.372m 7.210m 4.105m 8.411m 4.792m 9.529m 5.432m 10.562m 6.023m 11.508m 6.563m 12.367m 7.051m 13.138m 7.486m 13.821m 7.865m 14.417m 8.189m 14.930m 64.562m 117.094m 66.208m 119.708m 67.513m 121.667m 68.498m 123.055m 69.206m 124.020m 69.710m 124.711m 70.083m 125.232m 70.374m 125.650m 70.612m 126.000m 70.814m 126.305m 70.992m 126.577m 71.151m 126.823m 71.296m 127.050m 71.428m 127.260m 71.551m 127.457m 71.666m 127.643m 71.774m 127.818m 71.876m 127.986m 71.973m 128.147m 72.066m 128.304m 72.156m 128.458m 72.245m 128.614m 72.335m 128.776m 72.428m 128.948m 72.527m 129.140m 72.638m 129.361m 72.764m 129.621m 72.914m -3.133m -6.243m -12.974m -17.948m -17.964m -16.692m -15.152m -13.338m -11.313m -9.190m -6.999m -4.740m -2.410m -1.607f 2.391m 4.661m 6.817m 8.858m 10.784m 12.593m 14.284m 15.855m 17.306m 18.639m 19.856m 20.957m 21.944m 22.817m 23.575m 184.138m 187.874m 190.647m 192.621m 194.017m 195.034m 195.815m 196.447m 196.983m 197.453m 197.876m 198.263m 198.622m 198.958m 199.275m 199.576m 199.863m 200.138m 200.405m 200.667m 200.928m 201.194m 201.472m 201.774m 202.113m 202.503m DSP56364 Technical Data, Rev. 4 A-28 Freescale Semiconductor 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.00V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.00V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V 129.934m 130.316m 130.784m 131.358m 132.060m 132.912m 133.939m 135.166m 136.619m 138.324m 140.308m 142.597m 145.217m 148.192m 151.545m 155.300m 159.478m 164.097m 169.177m 174.734m 180.781m 187.333m 194.400m 201.993m 210.118m 73.093m 73.311m 73.579m 73.906m 74.304m 74.787m 75.368m 76.060m 76.878m 77.836m 78.948m 80.230m 81.694m 83.355m 85.224m 87.316m 89.640m 92.208m 95.029m 98.112m 101.465m 105.096m 109.009m 113.211m 117.705m 202.966m 203.524m 204.203m 205.033m 206.045m 207.276m 208.763m 210.544m 212.659m 215.149m 218.056m 221.419m 225.277m 229.669m 234.630m 240.194m 246.393m 253.255m 260.806m 269.070m 278.065m 287.810m 298.319m 309.602m 321.670m | [Pullup] | pullup in the table = pullup subtract power_clamp |Voltage I(typ) I(min) I(max) | -3.30V 132.979u 100.794u 170.075u -3.20V 138.984u 105.115u 178.000u -3.10V 145.559u 109.825u 186.702u -3.00V 152.789u 114.981u 196.300u -2.90V 160.778u 120.648u 206.941u -2.80V 169.651u 126.906u 218.803u -2.70V 179.562u 133.852u 232.110u -2.60V 190.706u 141.605u 247.141u -2.50V 203.326u 150.317u 264.253u -2.40V 217.736u 160.174u 283.910u -2.30V 234.344u 171.418u 306.723u -2.20V 253.692u 184.362u 333.513u -2.10V 276.513u 199.421u 365.415u -2.00V 303.830u 217.155u 404.033u -1.90V 337.102u 238.340u 451.722u -1.80V 378.494u 264.081u 512.067u -1.70V 431.351u 296.004u 590.810u -1.60V 501.113u 336.601u 697.730u -1.50V 597.240u 389.880u 850.877u -1.40V 737.641u 462.700u 1.087m -1.30V 960.395u 567.748u 1.497m -1.20V 1.361m 731.012u 2.348m -1.10V 2.237m 1.013m 4.712m -1.00V 4.644m 1.583m 10.148m -0.90V 8.090m 2.907m 12.062m DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-29 -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V -0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.00V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.00V 3.10V 3.20V 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.00V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 8.032m 4.727m 11.029m 7.118m 4.754m 9.778m 6.128m 4.128m 8.443m 5.109m 3.441m 7.052m 4.082m 2.746m 5.644m 3.056m 2.053m 4.233m 2.033m 1.363m 2.821m 1.014m 678.856u 1.410m 58.687e-18 58.622e-18 117.504e-18 -987.106u -655.604u -1.381m -1.928m -1.274m -2.709m -2.828m -1.859m -3.988m -3.685m -2.412m -5.216m -4.499m -2.931m -6.392m -5.269m -3.416m -7.516m -5.994m -3.866m -8.587m -6.673m -4.280m -9.602m -7.306m -4.658m -10.561m -7.890m -4.999m -11.461m -8.424m -5.301m -12.302m -8.907m -5.563m -13.081m -9.339m -65.539m -13.798m -110.103m -67.611m -154.438m -113.807m -69.311m -170.370m -117.010m -70.713m -176.323m -119.783m -71.893m -181.647m -122.195m -72.910m -186.387m -124.297m -73.804m -190.581m -126.131m -74.599m -194.261m -127.733m -75.311m -197.468m -129.139m -75.954m -200.255m -130.384m -76.540m -202.683m -131.498m -77.077m -204.814m -132.504m -77.575m -206.704m -133.423m -78.037m -208.399m -134.270m -78.470m -209.937m -135.057m -78.877m -211.346m -135.792m -79.261m -212.650m -136.483m -79.625m -213.864m -137.136m -79.971m -215.004m -137.756m -80.302m -216.079m -138.345m -80.617m -217.098m -138.908m -80.920m -218.067m -139.447m -81.210m -218.993m -139.964m -81.490m -219.880m -140.462m -81.761m -220.732m -140.943m -82.022m -221.552m -141.408m -82.277m -222.344m -141.860m -82.525m -223.112m -142.300m -82.769m -223.858m -142.733m -83.010m -224.586m -143.159m -83.250m -225.300m -143.585m -83.493m -226.006m -144.013m -83.740m -226.709m -144.449m -83.996m -227.417m DSP56364 Technical Data, Rev. 4 A-30 Freescale Semiconductor 4.70V 4.80V 4.90V 5.00V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.00V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V | [GND_clamp] | |Voltage | -3.30V -3.20V -3.10V -2.90V -2.80V -2.70V -2.60V -2.50V -2.40V -2.30V -2.20V -2.10V -1.90V -1.80V -1.70V -1.60V -1.50V -1.40V -1.30V -1.20V -1.10V -0.90V -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V -144.899m -84.265m -145.370m -84.551m -145.871m -84.861m -146.411m -85.200m -147.001m -85.575m -147.652m -85.993m -148.379m -86.464m -149.195m -86.995m -150.115m -87.597m -151.157m -88.280m -152.339m -89.054m -153.678m -89.930m -155.194m -90.921m -156.907m -92.038m -158.839m -93.294m -161.011m -94.701m -163.444m -96.273m -166.160m -98.023m -169.182m -99.963m -172.531m -102.106m -228.137m -228.879m -229.656m -230.481m -231.368m -232.336m -233.404m -234.592m -235.924m -237.426m -239.124m -241.046m -243.223m -245.685m -248.465m -251.595m -255.109m -259.041m -263.425m -268.293m I(typ) -2.637 -2.521 -2.406 -2.174 -2.059 -1.943 -1.828 -1.713 -1.598 -1.483 -1.368 -1.254 -1.026 -912.311m -799.377m -687.103m -575.715m -465.583m -357.354m -252.314m -153.494m -19.457m -3.535m -877.640u -156.838u -14.514u -780.351n -37.668n -1.699n -92.071p I(min) -1.514 -1.451 -1.387 -1.259 -1.195 -1.132 -1.068 -1.004 -941.073m -877.750m -814.544m -751.475m -625.847m -563.357m -501.149m -439.297m -377.904m -317.129m -257.221m -198.614m -142.138m -45.305m -16.226m -3.288m -397.909u -53.601u -6.086u -598.098n -55.739n -5.410n I(max) -3.063 -2.926 -2.789 -2.515 -2.378 -2.242 -2.105 -1.969 -1.833 -1.697 -1.561 -1.425 -1.155 -1.021 -886.904m -753.859m -621.897m -491.519m -363.667m -240.395m -127.373m -11.215m -4.650m -1.613m -271.662u -18.044u -560.308n -15.437n -411.332p -29.683p DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-31 0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.10V 3.20V 3.30V | [POWER_clamp] | |Voltage | 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.10V 5.20V 5.30V -27.709p -22.802p -19.598p -16.468p -13.353p -10.247p -7.147p -4.050p -955.896f 2.136p 8.315p 11.404p 14.492p 17.579p 20.666p 23.754p 26.841p 29.929p 33.018p 39.198p 42.291p 45.385p 48.483p 51.583p 54.673p 57.468p 59.647p 61.717p 65.859p 68.003p 72.601p -1.212n -18.939p -890.771p -16.163p -810.054p -13.516p -745.765p -10.874p -683.799p -8.234p -622.802p -5.595p -562.404p -2.956p -502.414p -318.962f -442.712p 2.318p -383.217p 4.954p -264.634p 10.227p -205.467p 12.862p -146.346p 15.498p -87.245p 18.133p -28.141p 20.768p 30.987p 23.404p 90.164p 26.039p 149.414p 28.674p 208.769p 31.310p 327.949p 36.581p 387.873p 39.216p 448.012p 41.852p 507.296p 44.489p 563.856p 47.125p 619.785p 49.762p 676.156p 52.401p 733.868p 55.040p 807.258p 57.675p 5.906n 61.928p 59.801n 63.585p 620.266n 65.236p I(typ) -27.709p -92.071p -1.699n -37.668n -780.351n -14.514u -156.838u -3.535m -19.457m -69.631m -153.494m -252.314m -357.354m -465.583m -575.715m -687.103m -912.311m -1.026 -1.140 I(min) -598.098n -6.086u -53.601u -397.909u -3.288m -16.226m -45.305m -142.138m -198.614m -257.221m -317.129m -377.904m -439.297m -501.149m -563.357m -625.847m -751.475m -814.544m -877.750m I(max) -10.874p -13.516p -16.163p -18.939p -29.683p -411.332p -15.437n -18.044u -271.662u -1.613m -4.650m -11.215m -43.562m -127.373m -240.395m -363.667m -621.897m -753.859m -886.904m DSP56364 Technical Data, Rev. 4 A-32 Freescale Semiconductor 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V -1.254 -941.073m -1.368 -1.004 -1.483 -1.068 -1.598 -1.132 -1.713 -1.195 -1.828 -1.259 -2.059 -1.387 -2.174 -1.451 -2.290 -1.514 -2.406 -1.578 -2.521 -1.642 -2.637 -1.706 -1.021 -1.155 -1.290 -1.425 -1.561 -1.697 -1.969 -2.105 -2.242 -2.378 -2.515 -2.652 | [Ramp] |Voltage I(typ) I(min) I(max) | dV/dt_f 1.99/104.603p 1.81/183.924p 2.18/69.643p | dV/dt_r 2.04/123.810p 1.85/215.062p 2.20/73.602p R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [Model] ipadex_i | "" Model_type Input Vinl = 0.8 Vinh = 2 | variable typ min max C_comp 2.92p 2.78p 2.96p | variable typ min max [Temperature Range] 40.0 0.0 120.0 | variable typ min max [Voltage Range] 3.30V 3.00V 3.60V | [GND_clamp] | |Voltage I(typ) I(min) I(max) | -3.30V -831.819m -473.616m -909.150m -3.20V -796.528m -454.528m -869.534m -3.10V -761.255m -435.451m -829.938m -2.90V -690.773m -397.335m -750.811m -2.80V -655.569m -378.299m -711.286m -2.70V -620.391m -359.279m -671.789m -2.60V -585.244m -340.277m -632.324m -2.50V -550.131m -321.295m -592.895m -2.40V -515.057m -302.336m -553.507m -2.30V -480.027m -283.402m -514.167m -2.20V -445.047m -264.496m -474.880m -2.10V -410.126m -245.624m -435.657m -1.90V -340.501m -207.998m -357.451m -1.80V -305.826m -189.259m -318.503m -1.70V -271.273m -170.582m -279.692m -1.60V -236.871m -151.981m -241.057m -1.50V -202.665m -133.474m -202.657m DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-33 -1.40V -1.30V -1.20V -1.10V -0.90V -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V 0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.10V 3.20V 3.30V -168.722m -135.151m -102.140m -70.064m -14.097m -1.307m -36.639u -903.944n -22.242n -567.014p -32.976p -18.575p -16.945p -15.630p -14.322p -13.014p -11.707p -10.399p -9.092p -7.784p -6.477p -5.169p -3.862p -1.246p 61.165f 1.369p 2.676p 3.984p 5.291p 6.599p 7.906p 9.214p 11.829p 13.137p 14.444p 15.752p 17.059p 18.367p 19.674p 20.982p 22.290p 24.905p 26.212p 27.520p -115.088m -96.861m -78.852m -61.160m -27.650m -13.160m -3.159m -256.975u -13.934u -730.372n -38.990n -2.810n -867.431p -713.428p -652.886p -597.227p -541.823p -486.432p -431.043p -375.653p -320.263p -264.873p -209.483p -98.704p -43.314p 12.076p 67.466p 122.856p 178.246p 233.635p 289.025p 344.415p 455.195p 510.585p 565.974p 621.364p 676.754p 732.144p 787.535p 842.946p 898.735p 1.163n 4.019n 57.671n -164.583m -126.991m -90.181m -54.834m -2.799m -53.501u -768.589n -10.997n -172.415p -16.888p -13.767p -12.822p -11.909p -10.996p -10.084p -9.171p -8.258p -7.345p -6.432p -5.520p -4.607p -3.694p -2.781p -955.508f -42.711f 870.085f 1.783p 2.696p 3.609p 4.521p 5.434p 6.347p 8.173p 9.085p 9.998p 10.911p 11.824p 12.736p 13.649p 14.562p 15.475p 17.301p 18.213p 19.126p | [POWER_clamp] | |Voltage I(typ) I(min) | 3.30V -15.630p -38.990n 3.40V -16.945p -730.372n 3.50V -18.575p -13.934u 3.60V -32.976p -256.975u 3.70V -567.014p -3.159m 3.80V -22.242n -13.160m I(max) -8.258p -9.171p -10.084p -10.996p -11.909p -12.822p DSP56364 Technical Data, Rev. 4 A-34 Freescale Semiconductor 3.90V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V -903.944n -1.307m -14.097m -39.803m -70.064m -102.140m -135.151m -168.722m -202.665m -236.871m -305.826m -340.501m -375.273m -410.126m -445.047m -480.027m -515.057m -550.131m -585.244m -655.569m -690.773m -726.003m -761.255m -796.528m -831.819m -27.650m -61.160m -78.852m -96.861m -115.088m -133.474m -151.981m -170.582m -189.259m -207.998m -245.624m -264.496m -283.402m -302.336m -321.295m -340.277m -359.279m -378.299m -397.335m -435.451m -454.528m -473.616m -492.715m -511.823m -530.941m -13.767p -172.415p -10.997n -768.589n -53.501u -2.799m -22.990m -54.834m -90.181m -126.991m -202.657m -241.057m -279.692m -318.503m -357.451m -396.509m -435.657m -474.880m -514.167m -592.895m -632.324m -671.789m -711.286m -750.811m -790.363m | |End model [Model] ipadm_3st | "" Model_type 3-state | variable typ min max C_comp 1.99p 1.86p 2.15p | variable typ min max [Temperature Range] 40.0 0.0 120.0 | variable typ min max [Voltage Range] 3.30V 3.00V 3.60V | [Pulldown] | pulldown in the table = pulldown subtract gnd_clamp |Voltage I(typ) I(min) I(max) | -3.30V -157.134u -99.256u -219.000u -3.20V -165.037u -104.127u -230.250u -3.10V -173.749u -109.479u -242.685u -3.00V -183.400u -115.386u -256.500u -2.90V -194.148u -121.936u -271.934u -2.80V -206.189u -129.240u -289.286u -2.70V -219.766u -137.431u -308.933u -2.60V -235.190u -146.680u -331.355u -2.50V -252.856u -157.199u -357.176u -2.40V -273.283u -169.265u -387.219u -2.30V -297.162u -183.236u -422.595u -2.20V -325.427u -199.590u -464.837u -2.10V -359.384u -218.976u -516.117u -2.00V -400.901u -242.299u -579.623u -1.90V -452.750u -270.851u -660.217u DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-35 -1.80V -1.70V -1.60V -1.50V -1.40V -1.30V -1.20V -1.10V -1.00V -0.90V -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V 0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.00V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.00V 3.10V 3.20V 3.30V 3.40V 3.50V 3.60V -519.217u -607.277u -729.045u -907.407u -1.191m -1.699m -2.799m -5.689m -10.416m -12.342m -11.672m -10.528m -9.204m -7.770m -6.286m -4.766m -3.214m -1.627m 32.755e-18 1.604m 3.124m 4.566m 5.928m 7.210m 8.411m 9.529m 10.562m 11.508m 12.367m 13.138m 13.821m 14.417m 14.930m 86.564m 88.497m 89.946m 90.974m 91.689m 92.200m 92.586m 92.895m 93.154m 93.380m 93.581m 93.764m 93.931m 94.087m 94.233m 94.370m 94.500m 94.624m 94.744m 94.859m 94.974m 95.089m -306.549u -765.681u -352.346u -909.270u -413.024u -1.115m -496.811u -1.434m -619.011u -1.987m -811.079u -3.133m -1.146m -6.243m -1.822m -12.974m -3.302m -17.948m -5.449m -17.964m -6.479m -16.692m -6.146m -15.152m -5.387m -13.338m -4.535m -11.313m -3.652m -9.190m -2.754m -6.999m -1.846m -4.740m -928.990u -2.410m 18.548e-18 -1.607f 910.814u 2.391m 1.775m 4.661m 2.595m 6.817m 3.372m 8.858m 4.105m 10.784m 4.792m 12.593m 5.432m 14.284m 6.023m 15.855m 6.563m 17.306m 7.051m 18.639m 7.486m 19.856m 7.865m 20.957m 8.189m 21.944m 47.725m 22.817m 48.943m 23.575m 49.908m 136.139m 50.637m 138.902m 51.160m 140.954m 51.534m 142.415m 51.810m 143.449m 52.024m 144.201m 52.201m 144.779m 52.351m 145.246m 52.482m 145.642m 52.600m 145.990m 52.706m 146.303m 52.804m 146.590m 52.895m 146.855m 52.980m 147.104m 53.060m 147.338m 53.135m 147.560m 53.207m 147.772m 53.276m 147.976m 53.343m 148.174m 53.408m 148.367m 53.475m 148.560m DSP56364 Technical Data, Rev. 4 A-36 Freescale Semiconductor 3.70V 3.80V 3.90V 4.00V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.00V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.00V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V 95.208m 95.336m 95.478m 95.641m 95.833m 96.065m 96.347m 96.693m 97.117m 97.636m 98.266m 99.024m 99.931m 101.005m 102.264m 103.730m 105.422m 107.357m 109.556m 112.034m 114.809m 117.897m 121.311m 125.066m 129.172m 133.642m 138.485m 143.709m 149.320m 155.326m 53.543m 53.617m 53.699m 53.792m 53.902m 54.035m 54.196m 54.394m 54.635m 54.930m 55.287m 55.716m 56.227m 56.831m 57.539m 58.361m 59.308m 60.391m 61.618m 63.000m 64.545m 66.263m 68.160m 70.245m 72.524m 75.002m 77.685m 80.578m 83.683m 87.004m 148.757m 148.963m 149.186m 149.436m 149.725m 150.067m 150.479m 150.981m 151.594m 152.342m 153.252m 154.350m 155.666m 157.230m 159.070m 161.218m 163.704m 166.555m 169.801m 173.468m 177.581m 182.163m 187.235m 192.816m 198.924m 205.573m 212.776m 220.544m 228.885m 237.805m | [Pullup] | pullup in the table = pullup subtract power_clamp |Voltage I(typ) I(min) I(max) | -3.30V 132.979u 100.794u 170.075u -3.20V 138.984u 105.115u 178.000u -3.10V 145.559u 109.825u 186.702u -3.00V 152.789u 114.981u 196.300u -2.90V 160.778u 120.648u 206.941u -2.80V 169.651u 126.906u 218.803u -2.70V 179.562u 133.852u 232.110u -2.60V 190.706u 141.605u 247.141u -2.50V 203.326u 150.317u 264.253u -2.40V 217.736u 160.174u 283.910u -2.30V 234.344u 171.418u 306.723u -2.20V 253.692u 184.362u 333.513u -2.10V 276.513u 199.421u 365.415u -2.00V 303.830u 217.155u 404.033u -1.90V 337.102u 238.340u 451.722u -1.80V 378.494u 264.081u 512.067u -1.70V 431.351u 296.004u 590.810u -1.60V 501.113u 336.601u 697.730u -1.50V 597.240u 389.880u 850.877u -1.40V 737.641u 462.700u 1.087m DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-37 -1.30V -1.20V -1.10V -1.00V -0.90V -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V -0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.00V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.00V 3.10V 3.20V 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.00V 4.10V 960.396u 567.748u 1.497m 1.361m 731.012u 2.348m 2.237m 1.013m 4.712m 4.644m 1.583m 10.148m 8.090m 2.907m 12.062m 8.032m 4.727m 11.029m 7.118m 4.754m 9.778m 6.128m 4.128m 8.443m 5.109m 3.441m 7.052m 4.082m 2.746m 5.644m 3.056m 2.053m 4.233m 2.033m 1.363m 2.821m 1.014m 678.856u 1.410m 58.687e-18 58.622e-18 117.504e-18 -987.106u -655.604u -1.381m -1.928m -1.274m -2.709m -2.828m -1.859m -3.988m -3.685m -2.412m -5.216m -4.499m -2.931m -6.392m -5.269m -3.416m -7.516m -5.994m -3.866m -8.587m -6.673m -4.280m -9.602m -7.306m -4.658m -10.561m -7.890m -4.999m -11.461m -8.424m -5.301m -12.302m -8.907m -5.563m -13.081m -9.339m -47.451m -13.837m -79.705m -48.954m -118.519m -82.391m -50.187m -123.324m -84.713m -51.203m -127.640m -86.724m -52.057m -131.501m -88.472m -52.794m -134.939m -89.996m -53.442m -137.982m -91.327m -54.017m -140.655m -92.489m -54.533m -142.987m -93.511m -54.999m -145.014m -94.415m -55.424m -146.781m -95.224m -55.814m -148.333m -95.955m -56.174m -149.709m -96.623m -56.510m -150.943m -97.238m -56.824m -152.063m -97.809m -57.119m -153.088m -98.343m -57.398m -154.036m -98.846m -57.662m -154.920m -99.320m -57.913m -155.749m -99.770m -58.152m -156.531m -100.198m -58.381m -157.272m -100.607m -58.601m -157.977m -100.998m -58.812m -158.650m -101.374m -59.015m -159.295m -101.735m -59.211m -159.914m -102.084m -59.401m -160.510m -102.422m -59.585m -161.086m -102.750m -59.766m -161.644m -103.070m -59.942m -162.186m DSP56364 Technical Data, Rev. 4 A-38 Freescale Semiconductor 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.00V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.00V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V | [GND_clamp] | |Voltage | -3.30V -3.20V -3.10V -2.90V -2.80V -2.70V -2.60V -2.50V -2.40V -2.30V -2.20V -2.10V -1.90V -1.80V -1.70V -1.60V -1.50V -1.40V -1.30V -1.20V -1.10V -0.90V -0.80V -0.70V -0.60V -103.384m -103.694m -104.002m -104.313m -104.629m -104.955m -105.296m -105.659m -106.050m -106.477m -106.949m -107.474m -108.064m -108.730m -109.483m -110.337m -111.305m -112.401m -113.640m -115.036m -116.606m -118.365m -120.329m -122.513m -124.935m -60.117m -60.291m -60.467m -60.647m -60.832m -61.027m -61.234m -61.459m -61.704m -61.975m -62.278m -62.619m -63.003m -63.439m -63.932m -64.492m -65.126m -65.843m -66.651m -67.560m -68.578m -69.715m -70.981m -72.384m -73.935m -162.715m -163.234m -163.747m -164.257m -164.770m -165.293m -165.831m -166.394m -166.991m -167.634m -168.334m -169.106m -169.965m -170.928m -172.012m -173.239m -174.627m -176.199m -177.978m -179.986m -182.247m -184.785m -187.626m -190.793m -194.311m I(typ) -2.165 -2.070 -1.975 -1.786 -1.691 -1.597 -1.503 -1.408 -1.314 -1.220 -1.126 -1.032 -845.771m -752.887m -660.410m -568.461m -477.221m -386.980m -298.248m -212.028m -130.668m -17.375m -2.837m -656.331u -116.521u I(min) -1.242 -1.190 -1.138 -1.033 -981.185m -929.174m -877.220m -825.330m -773.514m -721.779m -670.140m -618.610m -515.958m -464.892m -414.052m -363.494m -313.301m -263.597m -214.579m -166.582m -120.248m -40.029m -14.886m -3.014m -336.317u I(max) -2.500 -2.388 -2.277 -2.054 -1.942 -1.831 -1.720 -1.609 -1.498 -1.387 -1.276 -1.166 -945.908m -836.403m -727.373m -618.970m -511.430m -405.149m -300.867m -200.187m -107.496m -8.803m -3.451m -1.195m -201.636u DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-39 -0.50V -0.40V -0.30V -0.20V -0.10V 0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.10V 3.20V 3.30V | [POWER_clamp] | |Voltage | 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V -10.789u -580.051n -27.994n -1.269n -74.463p -26.215p -22.114p -19.278p -16.497p -13.726p -10.963p -8.203p -5.446p -2.691p 62.079f 5.566p 8.316p 11.067p 13.817p 16.567p 19.317p 22.067p 24.817p 27.568p 33.072p 35.825p 38.581p 41.339p 44.098p 46.849p 49.356p 51.378p 53.315p 57.193p 59.183p 62.959p -41.964u -13.420u -4.632u -416.799n -450.005n -11.484n -41.862n -311.158p -4.218n -27.092p -1.078n -18.737p -826.325p -16.303p -754.146p -13.966p -694.188p -11.632p -635.953p -9.300p -578.437p -6.968p -521.365p -4.637p -464.595p -2.307p -408.039p 22.980f -351.636p 2.353p -239.133p 7.011p -182.975p 9.340p -126.851p 11.669p -70.743p 13.998p -14.634p 16.327p 41.493p 18.656p 97.654p 20.985p 153.868p 23.313p 210.159p 25.642p 323.083p 30.300p 379.789p 32.629p 436.650p 34.958p 492.867p 37.288p 547.026p 39.618p 600.695p 41.948p 654.682p 44.279p 709.650p 46.611p 776.122p 48.939p 4.552n 52.772p 44.522n 54.319p 466.732n 55.861p I(typ) -26.215p -74.463p -1.269n -27.994n -580.051n -10.789u -116.521u -2.837m -17.375m -60.888m -130.668m -212.028m -298.248m -386.980m I(min) I(max) -450.005n -11.632p -4.632u -13.966p -41.964u -16.303p -336.317u -18.737p -3.014m -27.092p -14.886m -311.158p -40.029m -11.484n -120.248m -13.420u -166.582m -201.636u -214.579m -1.195m -263.597m -3.451m -313.301m -8.803m -363.494m -37.420m -414.052m -107.496m DSP56364 Technical Data, Rev. 4 A-40 Freescale Semiconductor 4.80V 4.90V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V -477.221m -568.461m -752.887m -845.771m -938.979m -1.032 -1.126 -1.220 -1.314 -1.408 -1.503 -1.691 -1.786 -1.881 -1.975 -2.070 -2.165 -464.892m -515.958m -618.610m -670.140m -721.779m -773.514m -825.330m -877.220m -929.174m -981.185m -1.033 -1.138 -1.190 -1.242 -1.294 -1.346 -1.399 -200.187m -300.867m -511.430m -618.970m -727.373m -836.403m -945.908m -1.056 -1.166 -1.276 -1.387 -1.609 -1.720 -1.831 -1.942 -2.054 -2.165 | [Ramp] |Voltage I(typ) I(min) I(max) | dV/dt_f 1.99/116.478p 1.81/206.384p 2.17/80.687p | dV/dt_r 2.02/147.722p 1.84/253.853p 2.19/93.030p R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [Model] ipadn_io | "" Model_type I/O Vinl = 0.8 Vinh = 2 | variable typ min max C_comp 2.03p 1.90p 2.18p | variable typ min max [Temperature Range] 40.0 0.0 120.0 | variable typ min max [Voltage Range] 3.30V 3.00V 3.60V | [Pulldown] | pulldown in the table = pulldown subtract gnd_clamp |Voltage I(typ) I(min) I(max) | -3.30V -157.134u -99.256u -219.000u -3.20V -165.037u -104.127u -230.250u -3.10V -173.749u -109.479u -242.685u -3.00V -183.400u -115.386u -256.500u -2.90V -194.148u -121.936u -271.934u -2.80V -206.189u -129.240u -289.286u -2.70V -219.766u -137.431u -308.933u -2.60V -235.190u -146.680u -331.355u -2.50V -252.856u -157.199u -357.176u -2.40V -273.283u -169.265u -387.219u -2.30V -297.162u -183.236u -422.595u -2.20V -325.427u -199.590u -464.837u DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-41 -2.10V -2.00V -1.90V -1.80V -1.70V -1.60V -1.50V -1.40V -1.30V -1.20V -1.10V -1.00V -0.90V -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V 0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.00V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.00V 3.10V 3.20V 3.30V -359.384u -400.901u -452.750u -519.217u -607.277u -729.045u -907.407u -1.191m -1.699m -2.799m -5.689m -10.416m -12.342m -11.672m -10.528m -9.204m -7.770m -6.286m -4.766m -3.214m -1.627m 32.755e-18 1.604m 3.124m 4.566m 5.928m 7.210m 8.411m 9.529m 10.562m 11.508m 12.367m 13.138m 13.821m 14.417m 14.930m 86.564m 88.497m 89.946m 90.974m 91.689m 92.200m 92.586m 92.895m 93.154m 93.380m 93.581m 93.764m 93.931m 94.087m 94.233m 94.370m 94.500m 94.624m 94.744m -218.976u -516.117u -242.299u -579.623u -270.851u -660.217u -306.549u -765.681u -352.346u -909.270u -413.024u -1.115m -496.811u -1.434m -619.011u -1.987m -811.079u -3.133m -1.146m -6.243m -1.822m -12.974m -3.302m -17.948m -5.449m -17.964m -6.479m -16.692m -6.146m -15.152m -5.387m -13.338m -4.535m -11.313m -3.652m -9.190m -2.754m -6.999m -1.846m -4.740m -928.990u -2.410m 18.548e-18 -1.607f 910.814u 2.391m 1.775m 4.661m 2.595m 6.817m 3.372m 8.858m 4.105m 10.784m 4.792m 12.593m 5.432m 14.284m 6.023m 15.855m 6.563m 17.306m 7.051m 18.639m 7.486m 19.856m 7.865m 20.957m 8.189m 21.944m 47.725m 22.817m 48.943m 23.575m 49.908m 136.139m 50.637m 138.902m 51.160m 140.954m 51.534m 142.415m 51.810m 143.449m 52.024m 144.201m 52.201m 144.779m 52.351m 145.246m 52.482m 145.642m 52.600m 145.990m 52.706m 146.303m 52.804m 146.590m 52.895m 146.855m 52.980m 147.104m 53.060m 147.338m 53.135m 147.560m 53.207m 147.772m 53.276m 147.976m DSP56364 Technical Data, Rev. 4 A-42 Freescale Semiconductor 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.00V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.00V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.00V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V 94.859m 94.974m 95.089m 95.208m 95.336m 95.478m 95.641m 95.833m 96.065m 96.347m 96.693m 97.117m 97.636m 98.266m 99.024m 99.931m 101.005m 102.264m 103.730m 105.422m 107.357m 109.556m 112.034m 114.809m 117.897m 121.311m 125.066m 129.172m 133.642m 138.485m 143.709m 149.320m 155.326m 53.343m 53.408m 53.475m 53.543m 53.617m 53.699m 53.792m 53.902m 54.035m 54.196m 54.394m 54.635m 54.930m 55.287m 55.716m 56.227m 56.831m 57.539m 58.361m 59.308m 60.391m 61.618m 63.000m 64.545m 66.263m 68.160m 70.245m 72.524m 75.002m 77.685m 80.578m 83.683m 87.004m 148.174m 148.367m 148.560m 148.757m 148.963m 149.186m 149.436m 149.725m 150.067m 150.479m 150.981m 151.594m 152.342m 153.252m 154.350m 155.666m 157.230m 159.070m 161.218m 163.704m 166.555m 169.801m 173.468m 177.581m 182.163m 187.235m 192.816m 198.924m 205.573m 212.776m 220.544m 228.885m 237.805m | [Pullup] | pullup in the table = pullup subtract power_clamp |Voltage I(typ) I(min) I(max) | -3.30V 132.979u 100.794u 170.075u -3.20V 138.984u 105.115u 178.000u -3.10V 145.559u 109.825u 186.702u -3.00V 152.789u 114.981u 196.300u -2.90V 160.778u 120.648u 206.941u -2.80V 169.651u 126.906u 218.803u -2.70V 179.562u 133.852u 232.110u -2.60V 190.706u 141.605u 247.141u -2.50V 203.326u 150.317u 264.253u -2.40V 217.736u 160.174u 283.910u -2.30V 234.344u 171.418u 306.723u -2.20V 253.692u 184.362u 333.513u -2.10V 276.513u 199.421u 365.415u -2.00V 303.830u 217.155u 404.033u -1.90V 337.102u 238.340u 451.722u -1.80V 378.494u 264.081u 512.067u -1.70V 431.351u 296.004u 590.810u DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-43 -1.60V -1.50V -1.40V -1.30V -1.20V -1.10V -1.00V -0.90V -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V -0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.00V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.00V 3.10V 3.20V 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 501.113u 336.601u 697.730u 597.240u 389.880u 850.877u 737.641u 462.700u 1.087m 960.396u 567.748u 1.497m 1.361m 731.012u 2.348m 2.237m 1.013m 4.712m 4.644m 1.583m 10.148m 8.090m 2.907m 12.062m 8.032m 4.727m 11.029m 7.118m 4.754m 9.778m 6.128m 4.128m 8.443m 5.109m 3.441m 7.052m 4.082m 2.746m 5.644m 3.056m 2.053m 4.233m 2.033m 1.363m 2.821m 1.014m 678.856u 1.410m 58.687e-18 58.622e-18 117.504e-18 -987.106u -655.604u -1.381m -1.928m -1.274m -2.709m -2.828m -1.859m -3.988m -3.685m -2.412m -5.216m -4.499m -2.931m -6.392m -5.269m -3.416m -7.516m -5.994m -3.866m -8.587m -6.673m -4.280m -9.602m -7.306m -4.658m -10.561m -7.890m -4.999m -11.461m -8.424m -5.301m -12.302m -8.907m -5.563m -13.081m -9.339m -47.451m -13.901m -79.705m -48.954m -118.519m -82.391m -50.187m -123.324m -84.713m -51.203m -127.640m -86.724m -52.057m -131.501m -88.472m -52.794m -134.939m -89.996m -53.442m -137.982m -91.327m -54.017m -140.655m -92.489m -54.533m -142.987m -93.511m -54.999m -145.014m -94.415m -55.424m -146.781m -95.224m -55.814m -148.333m -95.955m -56.174m -149.709m -96.623m -56.510m -150.943m -97.238m -56.824m -152.063m -97.809m -57.119m -153.088m -98.343m -57.398m -154.036m -98.846m -57.662m -154.920m -99.320m -57.913m -155.749m -99.770m -58.152m -156.531m -100.198m -58.381m -157.272m -100.607m -58.601m -157.977m -100.998m -58.812m -158.650m -101.374m -59.015m -159.295m -101.735m -59.211m -159.914m -102.084m -59.401m -160.510m DSP56364 Technical Data, Rev. 4 A-44 Freescale Semiconductor 3.90V 4.00V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.00V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.00V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V | [GND_clamp] | |Voltage | -3.30V -3.20V -3.10V -2.90V -2.80V -2.70V -2.60V -2.50V -2.40V -2.30V -2.20V -2.10V -1.90V -1.80V -1.70V -1.60V -1.50V -1.40V -1.30V -1.20V -1.10V -0.90V -102.422m -102.750m -103.070m -103.384m -103.694m -104.002m -104.313m -104.629m -104.955m -105.296m -105.659m -106.050m -106.477m -106.949m -107.474m -108.064m -108.730m -109.483m -110.337m -111.305m -112.401m -113.640m -115.036m -116.606m -118.365m -120.329m -122.513m -124.935m -59.585m -59.766m -59.942m -60.117m -60.291m -60.467m -60.647m -60.832m -61.027m -61.234m -61.459m -61.704m -61.975m -62.278m -62.619m -63.003m -63.439m -63.932m -64.492m -65.126m -65.843m -66.651m -67.560m -68.578m -69.715m -70.981m -72.384m -73.935m -161.086m -161.644m -162.186m -162.715m -163.234m -163.747m -164.257m -164.770m -165.293m -165.831m -166.394m -166.991m -167.634m -168.334m -169.106m -169.965m -170.928m -172.012m -173.239m -174.627m -176.199m -177.978m -179.986m -182.247m -184.785m -187.626m -190.793m -194.311m I(typ) -2.165 -2.070 -1.975 -1.786 -1.691 -1.597 -1.503 -1.408 -1.314 -1.220 -1.126 -1.032 -845.771m -752.887m -660.410m -568.461m -477.221m -386.980m -298.248m -212.028m -130.668m -17.375m I(min) -1.242 -1.190 -1.138 -1.033 -981.185m -929.174m -877.220m -825.330m -773.514m -721.779m -670.140m -618.610m -515.958m -464.892m -414.052m -363.494m -313.301m -263.597m -214.579m -166.582m -120.248m -40.029m I(max) -2.500 -2.388 -2.277 -2.054 -1.942 -1.831 -1.720 -1.609 -1.498 -1.387 -1.276 -1.166 -945.908m -836.403m -727.373m -618.970m -511.430m -405.149m -300.867m -200.187m -107.496m -8.803m DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-45 -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V 0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.10V 3.20V 3.30V -2.837m -656.331u -116.521u -10.789u -580.051n -27.994n -1.269n -74.463p -26.215p -22.114p -19.278p -16.497p -13.726p -10.963p -8.203p -5.446p -2.691p 62.079f 5.566p 8.316p 11.067p 13.817p 16.567p 19.317p 22.067p 24.817p 27.568p 33.072p 35.825p 38.581p 41.339p 44.098p 46.849p 49.356p 51.378p 53.315p 57.193p 59.183p 62.959p -14.886m -3.451m -3.014m -1.195m -336.317u -201.636u -41.964u -13.420u -4.632u -416.799n -450.005n -11.484n -41.862n -311.158p -4.218n -27.092p -1.078n -18.737p -826.325p -16.303p -754.146p -13.966p -694.188p -11.632p -635.953p -9.300p -578.437p -6.968p -521.365p -4.637p -464.595p -2.307p -408.039p 22.980f -351.636p 2.353p -239.133p 7.011p -182.975p 9.340p -126.851p 11.669p -70.743p 13.998p -14.634p 16.327p 41.493p 18.656p 97.654p 20.985p 153.868p 23.313p 210.159p 25.642p 323.083p 30.300p 379.789p 32.629p 436.650p 34.958p 492.867p 37.288p 547.026p 39.618p 600.695p 41.948p 654.682p 44.279p 709.650p 46.611p 776.122p 48.939p 4.552n 52.772p 44.522n 54.319p 466.732n 55.861p | [POWER_clamp] | |Voltage I(typ) I(min) I(max) | 3.30V -26.215p -450.005n -11.632p 3.40V -74.463p -4.632u -13.966p 3.50V -1.269n -41.964u -16.303p 3.60V -27.994n -336.317u -18.737p 3.70V -580.051n -3.014m -27.092p 3.80V -10.789u -14.886m -311.158p 3.90V -116.521u -40.029m -11.484n 4.10V -2.837m -120.248m -13.420u 4.20V -17.375m -166.582m -201.636u 4.30V -60.888m -214.579m -1.195m 4.40V -130.668m -263.597m -3.451m DSP56364 Technical Data, Rev. 4 A-46 Freescale Semiconductor 4.50V 4.60V 4.70V 4.80V 4.90V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V -212.028m -298.248m -386.980m -477.221m -568.461m -752.887m -845.771m -938.979m -1.032 -1.126 -1.220 -1.314 -1.408 -1.503 -1.691 -1.786 -1.881 -1.975 -2.070 -2.165 -313.301m -363.494m -414.052m -464.892m -515.958m -618.610m -670.140m -721.779m -773.514m -825.330m -877.220m -929.174m -981.185m -1.033 -1.138 -1.190 -1.242 -1.294 -1.346 -1.399 -8.803m -37.420m -107.496m -200.187m -300.867m -511.430m -618.970m -727.373m -836.403m -945.908m -1.056 -1.166 -1.276 -1.387 -1.609 -1.720 -1.831 -1.942 -2.054 -2.165 | [Ramp] |Voltage I(typ) I(min) I(max) | dV/dt_f 2.00/112.556p 1.82/199.937p 2.17/74.356p | dV/dt_r 2.02/146.245p 1.84/252.851p 2.20/93.872p R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [Model] ipadni_io | "" Model_type I/O Vinl = 0.8 Vinh = 2 | variable typ min max C_comp 2.01p 1.89p 2.17p | variable typ min max [Temperature Range] 40.0 0.0 120.0 | variable typ min max [Voltage Range] 3.30V 3.00V 3.60V | [Pulldown] | pulldown in the table = pulldown subtract gnd_clamp |Voltage I(typ) I(min) I(max) | -3.30V -157.134u -99.256u -219.000u -3.20V -165.037u -104.127u -230.250u -3.10V -173.749u -109.479u -242.685u -3.00V -183.400u -115.386u -256.500u -2.90V -194.148u -121.936u -271.934u -2.80V -206.189u -129.240u -289.286u -2.70V -219.766u -137.431u -308.933u -2.60V -235.190u -146.680u -331.355u -2.50V -252.856u -157.199u -357.176u DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-47 -2.40V -2.30V -2.20V -2.10V -2.00V -1.90V -1.80V -1.70V -1.60V -1.50V -1.40V -1.30V -1.20V -1.10V -1.00V -0.90V -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V 0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.00V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.00V -273.283u -297.162u -325.427u -359.384u -400.901u -452.750u -519.217u -607.277u -729.045u -907.407u -1.191m -1.699m -2.799m -5.689m -10.416m -12.342m -11.672m -10.528m -9.204m -7.770m -6.286m -4.766m -3.214m -1.627m 32.755e-18 1.604m 3.124m 4.566m 5.928m 7.210m 8.411m 9.529m 10.562m 11.508m 12.367m 13.138m 13.821m 14.417m 14.930m 86.564m 88.497m 89.946m 90.974m 91.689m 92.200m 92.586m 92.895m 93.154m 93.380m 93.581m 93.764m 93.931m 94.087m 94.233m 94.370m -169.265u -387.219u -183.236u -422.595u -199.590u -464.837u -218.976u -516.117u -242.299u -579.623u -270.851u -660.217u -306.549u -765.681u -352.346u -909.270u -413.024u -1.115m -496.811u -1.434m -619.011u -1.987m -811.079u -3.133m -1.146m -6.243m -1.822m -12.974m -3.302m -17.948m -5.449m -17.964m -6.479m -16.692m -6.146m -15.152m -5.387m -13.338m -4.535m -11.313m -3.652m -9.190m -2.754m -6.999m -1.846m -4.740m -928.990u -2.410m 18.548e-18 -1.607f 910.814u 2.391m 1.775m 4.661m 2.595m 6.817m 3.372m 8.858m 4.105m 10.784m 4.792m 12.593m 5.432m 14.284m 6.023m 15.855m 6.563m 17.306m 7.051m 18.639m 7.486m 19.856m 7.865m 20.957m 8.189m 21.944m 47.725m 22.817m 48.943m 23.575m 49.908m 136.139m 50.637m 138.902m 51.160m 140.954m 51.534m 142.415m 51.810m 143.449m 52.024m 144.201m 52.201m 144.779m 52.351m 145.246m 52.482m 145.642m 52.600m 145.990m 52.706m 146.303m 52.804m 146.590m 52.895m 146.855m 52.980m 147.104m 53.060m 147.338m DSP56364 Technical Data, Rev. 4 A-48 Freescale Semiconductor 3.10V 3.20V 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.00V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.00V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.00V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V 94.500m 94.624m 94.744m 94.859m 94.974m 95.089m 95.208m 95.336m 95.478m 95.641m 95.833m 96.065m 96.347m 96.693m 97.117m 97.636m 98.266m 99.024m 99.931m 101.005m 102.264m 103.730m 105.422m 107.357m 109.556m 112.034m 114.809m 117.897m 121.311m 125.066m 129.172m 133.642m 138.485m 143.709m 149.320m 155.326m 53.135m 53.207m 53.276m 53.343m 53.408m 53.475m 53.543m 53.617m 53.699m 53.792m 53.902m 54.035m 54.196m 54.394m 54.635m 54.930m 55.287m 55.716m 56.227m 56.831m 57.539m 58.361m 59.308m 60.391m 61.618m 63.000m 64.545m 66.263m 68.160m 70.245m 72.524m 75.002m 77.685m 80.578m 83.683m 87.004m 147.560m 147.772m 147.976m 148.174m 148.367m 148.560m 148.757m 148.963m 149.186m 149.436m 149.725m 150.067m 150.479m 150.981m 151.594m 152.342m 153.252m 154.350m 155.666m 157.230m 159.070m 161.218m 163.704m 166.555m 169.801m 173.468m 177.581m 182.163m 187.235m 192.816m 198.924m 205.573m 212.776m 220.544m 228.885m 237.805m | [Pullup] | pullup in the table = pullup subtract power_clamp |Voltage I(typ) I(min) I(max) | -3.30V 132.979u 100.794u 170.075u -3.20V 138.984u 105.115u 178.000u -3.10V 145.559u 109.825u 186.702u -3.00V 152.789u 114.981u 196.300u -2.90V 160.778u 120.648u 206.941u -2.80V 169.651u 126.906u 218.803u -2.70V 179.562u 133.852u 232.110u -2.60V 190.706u 141.605u 247.141u -2.50V 203.326u 150.317u 264.253u -2.40V 217.736u 160.174u 283.910u -2.30V 234.344u 171.418u 306.723u -2.20V 253.692u 184.362u 333.513u -2.10V 276.513u 199.421u 365.415u -2.00V 303.830u 217.155u 404.033u DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-49 -1.90V -1.80V -1.70V -1.60V -1.50V -1.40V -1.30V -1.20V -1.10V -1.00V -0.90V -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V -0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.00V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.00V 3.10V 3.20V 3.30V 3.40V 3.50V 337.102u 238.340u 451.722u 378.494u 264.081u 512.067u 431.351u 296.004u 590.810u 501.113u 336.601u 697.730u 597.240u 389.880u 850.877u 737.641u 462.700u 1.087m 960.396u 567.748u 1.497m 1.361m 731.012u 2.348m 2.237m 1.013m 4.712m 4.644m 1.583m 10.148m 8.090m 2.907m 12.062m 8.032m 4.727m 11.029m 7.118m 4.754m 9.778m 6.128m 4.128m 8.443m 5.109m 3.441m 7.052m 4.082m 2.746m 5.644m 3.056m 2.053m 4.233m 2.033m 1.363m 2.821m 1.014m 678.856u 1.410m 58.687e-18 58.622e-18 117.504e-18 -987.106u -655.604u -1.381m -1.928m -1.274m -2.709m -2.828m -1.859m -3.988m -3.685m -2.412m -5.216m -4.499m -2.931m -6.392m -5.269m -3.416m -7.516m -5.994m -3.866m -8.587m -6.673m -4.280m -9.602m -7.306m -4.658m -10.561m -7.890m -4.999m -11.461m -8.424m -5.301m -12.302m -8.907m -5.563m -13.081m -9.339m -47.451m -13.901m -79.705m -48.954m -118.519m -82.391m -50.187m -123.324m -84.713m -51.203m -127.640m -86.724m -52.057m -131.501m -88.472m -52.794m -134.939m -89.996m -53.442m -137.982m -91.327m -54.017m -140.655m -92.489m -54.533m -142.987m -93.511m -54.999m -145.014m -94.415m -55.424m -146.781m -95.224m -55.814m -148.333m -95.955m -56.174m -149.709m -96.623m -56.510m -150.943m -97.238m -56.824m -152.063m -97.809m -57.119m -153.088m -98.343m -57.398m -154.036m -98.846m -57.662m -154.920m -99.320m -57.913m -155.749m -99.770m -58.152m -156.531m -100.198m -58.381m -157.272m -100.607m -58.601m -157.977m -100.998m -58.812m -158.650m DSP56364 Technical Data, Rev. 4 A-50 Freescale Semiconductor 3.60V 3.70V 3.80V 3.90V 4.00V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.00V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.00V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V | [GND_clamp] | |Voltage | -3.30V -3.20V -3.10V -2.90V -2.80V -2.70V -2.60V -2.50V -2.40V -2.30V -2.20V -2.10V -1.90V -1.80V -1.70V -1.60V -1.50V -1.40V -1.30V -101.374m -101.735m -102.084m -102.422m -102.750m -103.070m -103.384m -103.694m -104.002m -104.313m -104.629m -104.955m -105.296m -105.659m -106.050m -106.477m -106.949m -107.474m -108.064m -108.730m -109.483m -110.337m -111.305m -112.401m -113.640m -115.036m -116.606m -118.365m -120.329m -122.513m -124.935m -59.015m -59.211m -59.401m -59.585m -59.766m -59.942m -60.117m -60.291m -60.467m -60.647m -60.832m -61.027m -61.234m -61.459m -61.704m -61.975m -62.278m -62.619m -63.003m -63.439m -63.932m -64.492m -65.126m -65.843m -66.651m -67.560m -68.578m -69.715m -70.981m -72.384m -73.935m -159.295m -159.914m -160.510m -161.086m -161.644m -162.186m -162.715m -163.234m -163.747m -164.257m -164.770m -165.293m -165.831m -166.394m -166.991m -167.634m -168.334m -169.106m -169.965m -170.928m -172.012m -173.239m -174.627m -176.199m -177.978m -179.986m -182.247m -184.785m -187.626m -190.793m -194.311m I(typ) -2.165 -2.070 -1.975 -1.786 -1.691 -1.597 -1.503 -1.408 -1.314 -1.220 -1.126 -1.032 -845.771m -752.887m -660.410m -568.461m -477.221m -386.980m -298.248m I(min) -1.242 -1.190 -1.138 -1.033 -981.185m -929.174m -877.220m -825.330m -773.514m -721.779m -670.140m -618.610m -515.958m -464.892m -414.052m -363.494m -313.301m -263.597m -214.579m I(max) -2.500 -2.388 -2.277 -2.054 -1.942 -1.831 -1.720 -1.609 -1.498 -1.387 -1.276 -1.166 -945.908m -836.403m -727.373m -618.970m -511.430m -405.149m -300.867m DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-51 -1.20V -1.10V -0.90V -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V 0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.10V 3.20V 3.30V -212.028m -130.668m -17.375m -2.837m -656.331u -116.521u -10.789u -580.051n -27.994n -1.269n -74.463p -26.215p -22.114p -19.278p -16.497p -13.726p -10.963p -8.203p -5.446p -2.691p 62.079f 5.566p 8.316p 11.067p 13.817p 16.567p 19.317p 22.067p 24.817p 27.568p 33.072p 35.825p 38.581p 41.339p 44.098p 46.849p 49.356p 51.378p 53.315p 57.193p 59.183p 62.959p -166.582m -120.248m -40.029m -14.886m -3.014m -336.317u -41.964u -4.632u -450.005n -41.862n -4.218n -1.078n -826.325p -754.146p -694.188p -635.953p -578.437p -521.365p -464.595p -408.039p -351.636p -239.133p -182.975p -126.851p -70.743p -14.634p 41.493p 97.654p 153.868p 210.159p 323.083p 379.789p 436.650p 492.867p 547.026p 600.695p 654.682p 709.650p 776.122p 4.552n 44.522n 466.732n -200.187m -107.496m -8.803m -3.451m -1.195m -201.636u -13.420u -416.799n -11.484n -311.158p -27.092p -18.737p -16.303p -13.966p -11.632p -9.300p -6.968p -4.637p -2.307p 22.980f 2.353p 7.011p 9.340p 11.669p 13.998p 16.327p 18.656p 20.985p 23.313p 25.642p 30.300p 32.629p 34.958p 37.288p 39.618p 41.948p 44.279p 46.611p 48.939p 52.772p 54.319p 55.861p | [POWER_clamp] | |Voltage I(typ) I(min) I(max) | 3.30V -26.215p -450.005n -11.632p 3.40V -74.463p -4.632u -13.966p 3.50V -1.269n -41.964u -16.303p 3.60V -27.994n -336.317u -18.737p 3.70V -580.051n -3.014m -27.092p 3.80V -10.789u -14.886m -311.158p 3.90V -116.521u -40.029m -11.484n 4.10V -2.837m -120.248m -13.420u DSP56364 Technical Data, Rev. 4 A-52 Freescale Semiconductor 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V -17.375m -60.888m -130.668m -212.028m -298.248m -386.980m -477.221m -568.461m -752.887m -845.771m -938.979m -1.032 -1.126 -1.220 -1.314 -1.408 -1.503 -1.691 -1.786 -1.881 -1.975 -2.070 -2.165 -166.582m -214.579m -263.597m -313.301m -363.494m -414.052m -464.892m -515.958m -618.610m -670.140m -721.779m -773.514m -825.330m -877.220m -929.174m -981.185m -1.033 -1.138 -1.190 -1.242 -1.294 -1.346 -1.399 -201.636u -1.195m -3.451m -8.803m -37.420m -107.496m -200.187m -300.867m -511.430m -618.970m -727.373m -836.403m -945.908m -1.056 -1.166 -1.276 -1.387 -1.609 -1.720 -1.831 -1.942 -2.054 -2.165 | [Ramp] |Voltage I(typ) I(min) I(max) | dV/dt_f 2.00/113.266p 1.82/197.371p 2.17/74.028p | dV/dt_r 2.02/147.014p 1.84/251.849p 2.20/93.411p R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [Model] ipado_3st | "" Model_type 3-state | variable typ min max C_comp 1.99p 1.86p 2.15p | variable typ min max [Temperature Range] 40.0 0.0 120.0 | variable typ min max [Voltage Range] 3.30V 3.00V 3.60V | [Pulldown] | pulldown in the table = pulldown subtract gnd_clamp |Voltage I(typ) I(min) I(max) | -3.30V -157.134u -99.256u -219.000u -3.20V -165.037u -104.127u -230.250u -3.10V -173.749u -109.479u -242.685u -3.00V -183.400u -115.386u -256.500u -2.90V -194.148u -121.936u -271.934u -2.80V -206.189u -129.240u -289.286u -2.70V -219.766u -137.431u -308.933u -2.60V -235.190u -146.680u -331.355u DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-53 -2.50V -2.40V -2.30V -2.20V -2.10V -2.00V -1.90V -1.80V -1.70V -1.60V -1.50V -1.40V -1.30V -1.20V -1.10V -1.00V -0.90V -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V 0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.00V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V -252.856u -273.283u -297.162u -325.427u -359.384u -400.901u -452.750u -519.217u -607.277u -729.045u -907.407u -1.191m -1.699m -2.799m -5.689m -10.416m -12.342m -11.672m -10.528m -9.204m -7.770m -6.286m -4.766m -3.214m -1.627m 32.755e-18 1.604m 3.124m 4.566m 5.928m 7.210m 8.411m 9.529m 10.562m 11.508m 12.367m 13.138m 13.821m 14.417m 14.930m 86.564m 88.497m 89.946m 90.974m 91.689m 92.200m 92.586m 92.895m 93.154m 93.380m 93.581m 93.764m 93.931m 94.087m 94.233m -157.199u -357.176u -169.265u -387.219u -183.236u -422.595u -199.590u -464.837u -218.976u -516.117u -242.299u -579.623u -270.851u -660.217u -306.549u -765.681u -352.346u -909.270u -413.024u -1.115m -496.811u -1.434m -619.011u -1.987m -811.079u -3.133m -1.146m -6.243m -1.822m -12.974m -3.302m -17.948m -5.449m -17.964m -6.479m -16.692m -6.146m -15.152m -5.387m -13.338m -4.535m -11.313m -3.652m -9.190m -2.754m -6.999m -1.846m -4.740m -928.990u -2.410m 18.548e-18 -1.607f 910.814u 2.391m 1.775m 4.661m 2.595m 6.817m 3.372m 8.858m 4.105m 10.784m 4.792m 12.593m 5.432m 14.284m 6.023m 15.855m 6.563m 17.306m 7.051m 18.639m 7.486m 19.856m 7.865m 20.957m 8.189m 21.944m 47.725m 22.817m 48.943m 23.575m 49.908m 136.139m 50.637m 138.902m 51.160m 140.954m 51.534m 142.415m 51.810m 143.449m 52.024m 144.201m 52.201m 144.779m 52.351m 145.246m 52.482m 145.642m 52.600m 145.990m 52.706m 146.303m 52.804m 146.590m 52.895m 146.855m 52.980m 147.104m DSP56364 Technical Data, Rev. 4 A-54 Freescale Semiconductor 3.00V 3.10V 3.20V 3.30V 3.40V 3.50V 3.60V 3.70V 3.80V 3.90V 4.00V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.00V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.00V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V 94.370m 94.500m 94.624m 94.744m 94.859m 94.974m 95.089m 95.208m 95.336m 95.478m 95.641m 95.833m 96.065m 96.347m 96.693m 97.117m 97.636m 98.266m 99.024m 99.931m 101.005m 102.264m 103.730m 105.422m 107.357m 109.556m 112.034m 114.809m 117.897m 121.311m 125.066m 129.172m 133.642m 138.485m 143.709m 149.320m 155.326m 53.060m 53.135m 53.207m 53.276m 53.343m 53.408m 53.475m 53.543m 53.617m 53.699m 53.792m 53.902m 54.035m 54.196m 54.394m 54.635m 54.930m 55.287m 55.716m 56.227m 56.831m 57.539m 58.361m 59.308m 60.391m 61.618m 63.000m 64.545m 66.263m 68.160m 70.245m 72.524m 75.002m 77.685m 80.578m 83.683m 87.004m 147.338m 147.560m 147.772m 147.976m 148.174m 148.367m 148.560m 148.757m 148.963m 149.186m 149.436m 149.725m 150.067m 150.479m 150.981m 151.594m 152.342m 153.252m 154.350m 155.666m 157.230m 159.070m 161.218m 163.704m 166.555m 169.801m 173.468m 177.581m 182.163m 187.235m 192.816m 198.924m 205.573m 212.776m 220.544m 228.885m 237.805m | [Pullup] | pullup in the table = pullup subtract power_clamp |Voltage I(typ) I(min) I(max) | -3.30V 132.979u 100.794u 170.075u -3.20V 138.984u 105.115u 178.000u -3.10V 145.559u 109.825u 186.702u -3.00V 152.789u 114.981u 196.300u -2.90V 160.778u 120.648u 206.941u -2.80V 169.651u 126.906u 218.803u -2.70V 179.562u 133.852u 232.110u -2.60V 190.706u 141.605u 247.141u -2.50V 203.326u 150.317u 264.253u -2.40V 217.736u 160.174u 283.910u -2.30V 234.344u 171.418u 306.723u -2.20V 253.692u 184.362u 333.513u -2.10V 276.513u 199.421u 365.415u DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-55 -2.00V -1.90V -1.80V -1.70V -1.60V -1.50V -1.40V -1.30V -1.20V -1.10V -1.00V -0.90V -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V -0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.00V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.00V 3.10V 3.20V 3.30V 3.40V 303.830u 217.155u 404.033u 337.102u 238.340u 451.722u 378.494u 264.081u 512.067u 431.351u 296.004u 590.810u 501.113u 336.601u 697.730u 597.240u 389.880u 850.877u 737.641u 462.700u 1.087m 960.396u 567.748u 1.497m 1.361m 731.012u 2.348m 2.237m 1.013m 4.712m 4.644m 1.583m 10.148m 8.090m 2.907m 12.062m 8.032m 4.727m 11.029m 7.118m 4.754m 9.778m 6.128m 4.128m 8.443m 5.109m 3.441m 7.052m 4.082m 2.746m 5.644m 3.056m 2.053m 4.233m 2.033m 1.363m 2.821m 1.014m 678.856u 1.410m 58.687e-18 58.622e-18 117.504e-18 -987.106u -655.604u -1.381m -1.928m -1.274m -2.709m -2.828m -1.859m -3.988m -3.685m -2.412m -5.216m -4.499m -2.931m -6.392m -5.269m -3.416m -7.516m -5.994m -3.866m -8.587m -6.673m -4.280m -9.602m -7.306m -4.658m -10.561m -7.890m -4.999m -11.461m -8.424m -5.301m -12.302m -8.907m -5.563m -13.081m -9.339m -47.451m -13.837m -79.705m -48.954m -118.519m -82.391m -50.187m -123.324m -84.713m -51.203m -127.640m -86.724m -52.057m -131.501m -88.472m -52.794m -134.939m -89.996m -53.442m -137.982m -91.327m -54.017m -140.655m -92.489m -54.533m -142.987m -93.511m -54.999m -145.014m -94.415m -55.424m -146.781m -95.224m -55.814m -148.333m -95.955m -56.174m -149.709m -96.623m -56.510m -150.943m -97.238m -56.824m -152.063m -97.809m -57.119m -153.088m -98.343m -57.398m -154.036m -98.846m -57.662m -154.920m -99.320m -57.913m -155.749m -99.770m -58.152m -156.531m -100.198m -58.381m -157.272m -100.607m -58.601m -157.977m DSP56364 Technical Data, Rev. 4 A-56 Freescale Semiconductor 3.50V 3.60V 3.70V 3.80V 3.90V 4.00V 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.00V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.00V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V | [GND_clamp] | |Voltage | -3.30V -3.20V -3.10V -2.90V -2.80V -2.70V -2.60V -2.50V -2.40V -2.30V -2.20V -2.10V -1.90V -1.80V -1.70V -1.60V -1.50V -1.40V -100.998m -101.374m -101.735m -102.084m -102.422m -102.750m -103.070m -103.384m -103.694m -104.002m -104.313m -104.629m -104.955m -105.296m -105.659m -106.050m -106.477m -106.949m -107.474m -108.064m -108.730m -109.483m -110.337m -111.305m -112.401m -113.640m -115.036m -116.606m -118.365m -120.329m -122.513m -124.935m -58.812m -59.015m -59.211m -59.401m -59.585m -59.766m -59.942m -60.117m -60.291m -60.467m -60.647m -60.832m -61.027m -61.234m -61.459m -61.704m -61.975m -62.278m -62.619m -63.003m -63.439m -63.932m -64.492m -65.126m -65.843m -66.651m -67.560m -68.578m -69.715m -70.981m -72.384m -73.935m -158.650m -159.295m -159.914m -160.510m -161.086m -161.644m -162.186m -162.715m -163.234m -163.747m -164.257m -164.770m -165.293m -165.831m -166.394m -166.991m -167.634m -168.334m -169.106m -169.965m -170.928m -172.012m -173.239m -174.627m -176.199m -177.978m -179.986m -182.247m -184.785m -187.626m -190.793m -194.311m I(typ) -2.165 -2.070 -1.975 -1.786 -1.691 -1.597 -1.503 -1.408 -1.314 -1.220 -1.126 -1.032 -845.771m -752.887m -660.410m -568.461m -477.221m -386.980m I(min) -1.242 -1.190 -1.138 -1.033 -981.185m -929.174m -877.220m -825.330m -773.514m -721.779m -670.140m -618.610m -515.958m -464.892m -414.052m -363.494m -313.301m -263.597m I(max) -2.500 -2.388 -2.277 -2.054 -1.942 -1.831 -1.720 -1.609 -1.498 -1.387 -1.276 -1.166 -945.908m -836.403m -727.373m -618.970m -511.430m -405.149m DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-57 -1.30V -1.20V -1.10V -0.90V -0.80V -0.70V -0.60V -0.50V -0.40V -0.30V -0.20V -0.10V 0.00V 0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V 1.70V 1.80V 1.90V 2.10V 2.20V 2.30V 2.40V 2.50V 2.60V 2.70V 2.80V 2.90V 3.10V 3.20V 3.30V -298.248m -212.028m -130.668m -17.375m -2.837m -656.331u -116.521u -10.789u -580.051n -27.994n -1.269n -74.463p -26.215p -22.114p -19.278p -16.497p -13.726p -10.963p -8.203p -5.446p -2.691p 62.079f 5.566p 8.316p 11.067p 13.817p 16.567p 19.317p 22.067p 24.817p 27.568p 33.072p 35.825p 38.581p 41.339p 44.098p 46.849p 49.356p 51.378p 53.315p 57.193p 59.183p 62.959p -214.579m -166.582m -120.248m -40.029m -14.886m -3.014m -336.317u -41.964u -4.632u -450.005n -41.862n -4.218n -1.078n -826.325p -754.146p -694.188p -635.953p -578.437p -521.365p -464.595p -408.039p -351.636p -239.133p -182.975p -126.851p -70.743p -14.634p 41.493p 97.654p 153.868p 210.159p 323.083p 379.789p 436.650p 492.867p 547.026p 600.695p 654.682p 709.650p 776.122p 4.552n 44.522n 466.732n -300.867m -200.187m -107.496m -8.803m -3.451m -1.195m -201.636u -13.420u -416.799n -11.484n -311.158p -27.092p -18.737p -16.303p -13.966p -11.632p -9.300p -6.968p -4.637p -2.307p 22.980f 2.353p 7.011p 9.340p 11.669p 13.998p 16.327p 18.656p 20.985p 23.313p 25.642p 30.300p 32.629p 34.958p 37.288p 39.618p 41.948p 44.279p 46.611p 48.939p 52.772p 54.319p 55.861p | [POWER_clamp] | |Voltage I(typ) I(min) I(max) | 3.30V -26.215p -450.005n -11.632p 3.40V -74.463p -4.632u -13.966p 3.50V -1.269n -41.964u -16.303p 3.60V -27.994n -336.317u -18.737p 3.70V -580.051n -3.014m -27.092p 3.80V -10.789u -14.886m -311.158p 3.90V -116.521u -40.029m -11.484n DSP56364 Technical Data, Rev. 4 A-58 Freescale Semiconductor 4.10V 4.20V 4.30V 4.40V 4.50V 4.60V 4.70V 4.80V 4.90V 5.10V 5.20V 5.30V 5.40V 5.50V 5.60V 5.70V 5.80V 5.90V 6.10V 6.20V 6.30V 6.40V 6.50V 6.60V -2.837m -17.375m -60.888m -130.668m -212.028m -298.248m -386.980m -477.221m -568.461m -752.887m -845.771m -938.979m -1.032 -1.126 -1.220 -1.314 -1.408 -1.503 -1.691 -1.786 -1.881 -1.975 -2.070 -2.165 -120.248m -166.582m -214.579m -263.597m -313.301m -363.494m -414.052m -464.892m -515.958m -618.610m -670.140m -721.779m -773.514m -825.330m -877.220m -929.174m -981.185m -1.033 -1.138 -1.190 -1.242 -1.294 -1.346 -1.399 -13.420u -201.636u -1.195m -3.451m -8.803m -37.420m -107.496m -200.187m -300.867m -511.430m -618.970m -727.373m -836.403m -945.908m -1.056 -1.166 -1.276 -1.387 -1.609 -1.720 -1.831 -1.942 -2.054 -2.165 | [Ramp] |Voltage I(typ) I(min) I(max) | dV/dt_f 1.99/130.331p 1.81/220.000p 2.17/83.712p | dV/dt_r 2.03/153.657p 1.84/260.814p 2.20/92.663p R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [End] DSP56364 Technical Data, Rev. 4 Freescale Semiconductor A-59 NOTES DSP56364 Technical Data, Rev. 4 A-60 Freescale Semiconductor Index A ac electrical characteristics 4 out of page and refresh timings 11 wait states 31 15 wait states 33 4 wait states 27 8 wait states 29 Page mode read accesses 26 wait states selection guide 17 write accesses 25 Page mode timings 1 wait state 17 2 wait states 20 3 wait states 22 4 wait states 23 refresh access 37 B Boundary Scan (JTAG Port) timing diagram 54 bus external address 4 external data 4 C Clock 4 clock external 4 operation 6 clocks internal 4 configuration 3 E electrical design considerations 3 emory 3 Enhanced Serial Audio Interface 9 ESAI 9 receiver timing 51, 52 timings 47 transmitter timing 50 EXTAL jitter 4 external address bus 4 external bus control 4, 5 external clock operation 4 external data bus 4 external interrupt timing (negative edge-triggered) 11 external level-sensitive fast interrupt timing 10 external memory access (DMA Source) timing 12 External Memory Expansion Port 4, 12 D dc electrical characteristics 3 design considerations electrical 3 PLL 4 power consumption 3 thermal 1 DRAM out of page wait states selection guide 27 DSP56364 Technical Data, Rev. 4 Freescale Semiconductor Index-1 F functional signal groups 1 O OnCE module 12 operating mode select timing 11 G GPIO timing 52 Ground 3 PLL 3 P package TQFP description 1, 3 Peripheral modules 3 Phase Lock Loop 6 PLL 4, 6 Characteristics 6 performance issues 4 PLL design considerations 4 PLL performance issues 4 Port A 4 Port C 9 Power 2 power consumption design considerations 3 I internal clocks 4 interrupt and mode control 6 interrupt control 6 interrupt timing 7 external level-sensitive fast 10 external negative edge-triggered 11 J Jitter 4 JTAG 12 JTAG Port timing 53, 54 R recovery from Stop state using IRQA 11, 12 RESET 6 Reset timing 7, 10 S M maximum ratings 1, 2 Memory 3 Memory Configuration 3 mode control 6 Mode select timing 7 Serial Audio Interface (ESAI) 3 Serial Host Interface 7 Serial Host Interface (SHI) 3 SHI 7 signal groupings 1 signals 1 SRAM DSP56364 Technical Data, Rev. 4 Index-2 Freescale Semiconductor read and write accesses 12 Stop state recovery from 11, 12 Stop timing 7 supply voltage 2 T Test Access Port timing diagram 55 Test Clock (TCLK) input timing diagram 54 thermal characteristics 2 thermal design considerations 1 Timing Enhanced Serial Audio Interface (ESAI) 50 General Purpose I/O (GPIO) Timing 47 OnCETM (On Chip Emulator) Timing 47 Serial Host Interface (SHI) SPI Protocol Timing 37 Serial Host Interface (SHI) Timing 37 timing interrupt 7 mode select 7 Reset 7 Stop 7 TQFP pin list by number 3 pin-out drawing (top) 1 DSP56364 Technical Data, Rev. 4 Freescale Semiconductor Index-3 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2006. All rights reserved. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. Document Number: DSP56364 Rev. 4 08/2006 |
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